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CY5137-1X07I

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Document Number: 001-90233 Rev. *K Page 16 of 25
CY51X7
Figure 10. HCSL: Single-ended Measurement Points for
Absolute Crossing Point
Figure 11. HCSL: Single-ended Measurement Points for
Delta Crossing Point
Figure 12. HCSL: Differential Measurement Points for Rise
and Fall Time
Figure 13. HCSL: Differential Measurement Points for
Ringback
Figure 14. I
2
C Bus Timing Specifications
V
MAX
=1.15V
REFCLKͲ
V
CROSSMAX
=550mV
V
CROSSMIN
=250mV
REFCLK+
V
MIN
=Ͳ0.30V
REFCLKͲ
REFCLK+
V
CROSSDELTA
=140mV
V
IH
=+150mV
V
IL
=Ͳ150mV
0.0V
REFCLK+
minus
RisingEdgeRate FallingEdgeRate
V
IH
=+150mV
V
RB
=+100mV
V
RB
=Ͳ100mV
V
IL
=Ͳ150mV
REFCLK+
minus
T
STABLE
T
STABLE
V
RB
V
RB
SDA
SCL
S
Sr
PS
t
f
t
r
t
LOW
t
HD;STA
t
HD;DAT
t
HIGH
t
SU;DAT
t
f
t
SU;STA
t
HD;STA
t
SU;STO
t
r
t
BUF
Document Number: 001-90233 Rev. *K Page 17 of 25
CY51X7
Phase Noise Plots
Figure 15. Typical Phase Noise at 156.25 MHz (12 kHz–20 MHz)
Document Number: 001-90233 Rev. *K Page 18 of 25
CY51X7
Figure 16. Typical Phase Noise at 622.08 MHz (12 kHz–20 MHz)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

CY5137-1X07I

Mfr. #:
Buy CY5137-1X07I
Manufacturer:
Cypress Semiconductor
Description:
Clock Generators & Support Products Programmable Clocks
Lifecycle:
New from this manufacturer.
Delivery:
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