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LTC1419
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APPLICATIONS INFORMATION
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DIGITAL INTERFACE
The A/D converter is designed to interface with micropro-
cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a
conversion.
Internal Clock
The A/D converter has an internal clock that eliminates the
need of synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 0.95µs and a maximum conversion time over the
full operating temperature range of 1.15µs. No external
adjustments are required. The guaranteed maximum
acquisition time is 300ns. In addition, a throughput time of
1.25µs and a minimum sampling rate of 800ksps are
guaranteed.
Power Shutdown
The LTC1419 provides two power shutdown modes, nap
and sleep, to save power during inactive periods. The nap
t
3
CS
SHDN
1419 F14a
Figure 14a. CS to SHDN Timing
mode reduces the power by 95% and leaves only the
digital logic and reference powered up. The wake-up time
from nap to active is 400ns. In sleep mode, the reference
is shut down and only a small current remains, about
250µA. Wake-up time from sleep mode is much slower
since the reference circuit must power up and settle to
0.005% for full 14-bit accuracy. Sleep mode wake-up
time is dependent on the value of the capacitor connected
to the REFCOMP (Pin 4). The wake-up time is 10ms with
the recommended 10µF capacitor.
Shutdown is con-
trolled by Pin 21 (SHDN); the ADC is in shutdown when it
is low. The shutdown mode is selected with Pin 20 (CS);
low selects nap.
Figure 13d. Suggested Evaluation Circuit Board—Solder Side Layout
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LTC1419
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APPLICATIONS INFORMATION
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In slow memory and ROM modes (Figures 19 and 20), CS
is tied low and CONVST and RD are tied together. The MPU
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
In slow memory mode, the processor applies a logic low
to RD (= CONVST), starting the conversion. BUSY goes
low, forcing the processor into a WAIT state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results ap-
pear on the data outputs; BUSY goes high, releasing the
processor and the processor takes RD (= CONVST) back
high and reads the new conversion data.
In ROM mode, the processor takes RD (= CONVST) low,
starting a conversion and reading the previous conversion
result. After the conversion is complete, the processor can
read the new result and initiate another conversion.
t
3
SHDN
CONVST
1419 F14b
Figure 14b. SHDN to CONVST Wake-Up Timing
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A logic “0”
applied to the CONVST pin will start a conversion after the
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY
is low during a conversion.
Figures 16 through 20 show several different modes of
operation. In modes 1a and 1b (Figures 16 and 17), CS
and RD are both tied low. The falling edge of CONVST
starts the conversion. The data outputs are always enabled
and data can be latched with the BUSY rising edge. Mode
1a shows operation with a narrow logic low CONVST
pulse. Mode 1b shows a narrow logic high CONVST pulse.
In mode 2 (Figure 18), CS is tied low. The falling edge of
the CONVST signal again starts the conversion. Data
outputs are in three-state until read by the MPU with the
RD signal. Mode 2 can be used for operation with a shared
MPU databus.
t
1
CS
RD
1419 F15
Figure 15. CS to CONVST Set-Up Timing
Figure 16. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
DATA (N – 1)
DB13 TO DB0
CONVST
CS = RD = 0
BUSY
1419 F16
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5
t
CONV
t
6
t
8
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7
DATA
(SAMPLE N)
(CONVST = )
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LTC1419
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APPLICATIONS INFORMATION
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DATA (N – 1)
DB13 TO DB0
CONVST
BUSY
1419 F17
t
CONV
t
6
t
13
t
7
CS = RD = 0
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
DATA
t
5
t
6
t
6
t
8
Figure 17. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST = )
RD = CONVST
CS = 0
BUSY
1419 F19
t
CONV
(SAMPLE N)
t
6
DATA (N – 1)
DB13 TO DB0
DATA
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
DATA N
DB13 TO DB0
t
11
t
8
t
10
t
7
Figure 19. Slow Memory Mode Timing
CONVST
CS = 0
BUSY
1419 F18
t
5
t
CONV
(SAMPLE N)
t
8
t
13
t
6
t
9
t
12
DATA N
DB13 TO DB0
t
11
t
10
RD
DATA
Figure 18. Mode 2. CONVST Starts a Conversion. Data is Read by RD

LTC1419IG#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 800ksps 14-Bit Parallel ADC
Lifecycle:
New from this manufacturer.
Delivery:
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