7
LTC1419
1419fb
Load Circuits for Access Timing
Load Circuits for Output Float Delay
TEST CIRCUITS
1k C
L
C
L
DBN
(A) Hi-Z TO V
OH
(B) Hi-Z TO V
O
DBN
1k
5V
1419 TC01
1k 100pF 100pF
DBN
(A) V
OH
TO Hi-Z (B) V
OL
TO Hi-Z
DBN
1k
5V
1419 TC02
APPLICATIONS INFORMATION
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CONVERSION DETAILS
The LTC1419 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs (please refer to Digital Interface section for
the data format).
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion, the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun, it cannot be restarted.
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit (LSB).
Referring to Figure 1, the +A
IN
and –A
IN
inputs are con-
nected to the sample-and-hold capacitors (C
SAMPLE
) dur-
ing the acquire phase and the comparator offset is nulled by
the zeroing switches. In this acquire phase, a minimum
delay of 200ns will provide enough time for the sample-
and-hold capacitors to acquire the analog signal. During
the convert phase, the comparator zeroing switches open,
putting the comparator into compare mode. The input
switches the C
SAMPLE
capacitors to ground, transferring
the differential analog input charge onto the summing
junction. This input charge is successively compared with
the binary weighted charges supplied by the differential
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the differential
DAC output balances the +A
IN
and –A
IN
input charges.
The SAR contents (a 14-bit data word) which represents
the difference of +A
IN
and –A
IN
are loaded into the 14-bit
output latches.
DYNAMIC PERFORMANCE
The LTC1419 has excellent high speed sampling capabil-
ity. FFT (Fast Fourier Transform) test techniques are used
to test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
Figure 1. Simplified Block Diagram
COMP
+C
SAMPLE
–C
DAC
D13
D0
ZEROING SWITCHES
HOLD
HOLD
+A
IN
–A
IN
+C
DAC
–C
SAMPLE
14
1419 F01
+
SAR
OUTPUT
LATCHES
+V
DAC
–V
DAC
HOLD
HOLD
SAMPLE
SAMPLE
8
LTC1419
1419fb
APPLICATIONS INFORMATION
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frequencies outside the fundamental. Figure 2 shows a
typical LTC1419 FFT plot.
Effective Number of Bits
The effective number of bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) – 1.76]/6.02
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 800kHz, the LTC1419 maintains near ideal ENOBs
up to the Nyquist input frequency of 400kHz (refer to
Figure 3).
FREQUENCY (kHz)
0
AMPLITUDE (dB)
–60
–40
–20
300
1419 F02a
–80
–100
100 200 400
250
50 150 350
–120
–140
0
f
SAMPLE
= 800kHz
f
IN
= 99.804687kHz
SFDR = 98dB
THD = –93.3dB
Figure 2a. LTC1419 Nonaveraged, 4096 Point FFT,
Input Frequency = 100kHz
FREQUENCY (kHz)
0
AMPLITUDE (dB)
–60
–40
–20
300
1419 F02b
–80
–100
100 200 400
250
50 150 350
–120
–140
0
f
SAMPLE
= 800kHz
f
IN
= 375kHz
SFDR = 88.3dB
SINAD = 80.1
Figure 2b. LTC1419 Nonaveraged, 4096 Point FFT,
Input Frequency = 375kHz
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 2 shows a typical spectral content with
a 800kHz sampling rate and a 100kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 400kHz.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
THD Log
VVV Vn
V
=
+++
20
234
1
222 2
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
second through nth harmonics. THD vs Input Frequency is
shown in Figure 4. The LTC1419 has good distortion
performance up to the Nyquist frequency and beyond.
INPUT FREQUENCY (Hz)
1k
EFFECTIVE BITS
SIGNAL/(NOISE + DISTORTION) (dB)
14
13
12
11
10
9
8
7
6
5
4
3
2
86
80
74
68
62
10k 100k
1419 TA02
1M 2M
f
SAMPLE
= 800kHz
Figure 3. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
9
LTC1419
1419fb
APPLICATIONS INFORMATION
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Figure 4. Distortion vs Input Frequency
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3,
etc. For example, the 2nd order IMD terms include
(fa + fb). If the two input sine waves are equal in magni-
tude, the value (in decibels) of the 2nd order IMD products
can be expressed by the following formula:
IMD fa fb Log+
()
= 20
Amplitude at (fa + fb)
Amplitude at fa
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal.
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 77dB (12.5 effective bits).
The LTC1419 has been designed to optimize input band-
width, allowing the ADC to undersample input signals with
frequencies above the converter’s Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.
Driving the Analog Input
The differential analog inputs of the LTC1419 are easy to
drive. The inputs may be driven differentially or as a single-
ended input (i.e., the –A
IN
input is grounded). The +A
IN
and – A
IN
inputs are sampled at the same instant. Any
unwanted signal that is common mode to both inputs will
be reduced by the common mode rejection of the sample-
and-hold circuit. The inputs draw only one small current
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion, the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low, then the LTC1419
inputs can be driven directly. As source impedance in-
creases so will acquisition time (see Figure 6). For mini-
mum acquisition time with high source impedance, a
buffer amplifier should be used. The only requirement is
Figure 5. Intermodulation Distortion Plot
FREQUENCY (kHz)
0
120
AMPLITUDE (dB)
100
–80
–60
–40
100 200
300
400
1419 G05
–20
0
50 150
250
350
f
SAMPLE
= 800kHz
f
IN1
= 95.8984375kHz
f
IN2
= 104.1015625kHz
INPUT FREQUENCY (Hz)
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
100
110
1419 G03
THD
2ND
3RD
1k 100k 1M 2M10k

LTC1419IG#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 800ksps 14-Bit Parallel ADC
Lifecycle:
New from this manufacturer.
Delivery:
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