4
LTC1419
1419fb
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended +A
IN
input with – A
IN
grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from 0.5LSB
when the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling edge of CONVST starts a conversion. If CONVST
returns high at a critical point during the conversion it can create small
errors. For best performance ensure that CONVST returns high either
within 650ns after the start of the conversion or after BUSY rises.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
P
DIS
Power Dissipation 150 240 mW
Nap Mode SHDN = 0V, CS = 0V 7.5 12 mW
Sleep Mode SHDN = 0V, CS = 5V 1.2 mW
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE(MAX)
Maximum Sampling Frequency 800 kHz
t
CONV
Conversion Time 950 1150 ns
t
ACQ
Acquisition Time 90 300 ns
t
ACQ + CONV
Acquisition + Conversion Time 1040 1250 ns
t
1
CS to RD Setup Time (Notes 9, 10) 0ns
t
2
CS to CONVST Setup Time (Notes 9, 10) 40 ns
t
3
CS to SHDN Setup Time (Notes 9, 10) 40 ns
t
4
SHDN to CONVST Wake-Up Time (Note 10) 400 ns
t
5
CONVST Low Time (Notes 10, 11) 40 ns
t
6
CONVST to BUSY Delay C
L
= 25pF 20 ns
50 ns
t
7
Data Ready Before BUSY 20 50 ns
15 ns
t
8
Delay Between Conversions (Note 10) 40 ns
t
9
Wait Time RD After BUSY (Note 9) –5 ns
t
10
Data Access Time After RD C
L
= 25pF 15 25 ns
35 ns
C
L
= 100pF 20 35 ns
50 ns
t
11
Bus Relinquish Time 10 20 ns
0°C T
A
70°C 25 ns
–40°C T
A
85°C 30 ns
t
12
RD Low Time t
10
ns
t
13
CONVST High Time 40 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below V
SS
or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V
SS
or above V
DD
without latchup.
Note 4: When these pin voltages are taken below V
SS
, they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below V
SS
without latchup. These pins are not clamped
to V
DD
.
Note 5: V
DD
= 5V, V
SS
= – 5V, f
SAMPLE
= 800kHz, t
r
= t
f
= 5ns unless
otherwise specified.
The denotes specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. (Note 5)
POWER REQUIRE E TS
WU
The denotes specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 5)
TI I G CHARACTERISTICS
UW
5
LTC1419
1419fb
TYPICAL PERFORMANCE CHARACTERISTICS
U
W
S/(N + D) vs Input Frequency
and Amplitude Distortion vs Input Frequency
Spurious-Free Dynamic Range
vs Input Frequency
Differential Nonlinearity
vs Output Code
Integral Nonlinearity
vs Output Code
Input Common Mode Rejection
vs Input Frequency
INPUT FREQUENCY (Hz)
SIGNAL/(NOISE + DISTORTION) (dB)
90
80
70
60
50
40
30
20
10
0
1k 100k 1M 2M
1419 G01
10k
V
IN
= 0dB
V
IN
= –20dB
V
IN
= –60dB
INPUT FREQUENCY (Hz)
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
100
110
1419 G03
THD
2ND
3RD
1k 100k 1M 2M10k
Signal-to-Noise Ratio
vs Input Frequency
INPUT FREQUENCY (Hz)
SIGNAL-TO -NOISE RATIO (dB)
1k
0
90
80
70
60
50
40
30
20
10
1419 G02
100k 1M 2M10k
Intermodulation Distortion Plot
INPUT FREQUENCY (Hz)
10k
SPURIOUS-FREE DYNAMIC RANGE (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
100k 1M 2M
1419 G04
FREQUENCY (kHz)
0
120
AMPLITUDE (dB)
100
–80
–60
–40
100 200
300
400
1419 G05
–20
0
50 150
250
350
f
SAMPLE
= 800kHz
f
IN1
= 95.8984375kHz
f
IN2
= 104.1015625kHz
OUTPUT CODE
0
1.0
DNL ERROR (LSBs)
0.5
0
0.5
1.0
4096 8192
1419 G06
12288 16384
Power Supply Feedthrough
vs Ripple Frequency
OUTPUT CODE
0
1.0
INL ERROR (LSBs)
0.5
0
0.5
1.0
4096 8192
1419 G07
12288 16384
RIPPLE FREQUENCY (Hz)
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
100
1k 100k 1M 2M
1419 G08
10k
V
SS
DGND
V
DD
INPUT FREQUENCY (Hz)
1
COMMON MODE REJECTION (dB)
80
70
60
50
40
30
20
10
0
10 100
1419 G09
1000 10000
6
LTC1419
1419fb
CONVST (Pin 23): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
CS (Pin 24): Chip Select. The input must be low for the
ADC to recognize CONVST and RD inputs. CS also sets
the shutdown mode when SHDN goes low. CS and
SHDN low select the quick wake-up nap mode. CS high
and SHDN low select sleep mode.
BUSY (Pin 25): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data
valid on the rising edge of BUSY.
V
SS
(Pin 26):5V Negative Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF or 10µF
ceramic.
DV
DD
(Pin 27): 5V Positive Supply. Short to Pin 28.
AV
DD
(Pin 28): 5V Positive Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF or 10µF
ceramic.
+A
IN
(Pin 1): ±2.5V Positive Analog Input.
–A
IN
(Pin 2): ±2.5V Negative Analog Input.
V
REF
(Pin 3): 2.5V Reference Output. Bypass to AGND
with 1µF.
REFCOMP (Pin 4): 4.06V Reference Output. Bypass to
AGND with 10µF tantalum in parallel with 0.1µF or 10µF
ceramic.
AGND (Pin 5): Analog Ground.
D13 to D6 (Pins 6 to 13): Three-State Data Outputs. The
output format is 2’s complement.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
D5 to D0 (Pins 15 to 20): Three-State Data Outputs. The
output format is 2’s complement.
SHDN (Pin 21): Power Shutdown Input. Low selects
shutdown. Shutdown mode selected by CS. CS = 0 for
nap mode and CS = 1 for sleep mode.
RD (Pin 22): Read Input. This enables the output
drivers when CS is low.
14-BIT CAPACITIVE DAC
COMPREF AMP
2.5V REF
REFCOMP
(4.096V)
C
SAMPLE
C
SAMPLE
D13
D0
BUSY
CONTROL LOGIC
CSCONVST RDSHDN
INTERNAL
CLOCK
ZEROING SWITCHES
DV
DD
V
SS
AV
DD
+A
IN
–A
IN
V
REF
AGND
DGND
14
1419 BD
+
SUCCESSIVE APPROXIMATION
REGISTER
OUTPUT LATCHES
2k
FU CTIO AL BLOCK DIAGRA
UU W
UU
U
PI FU CTIO S

LTC1419IG#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 800ksps 14-Bit Parallel ADC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union