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AD7858ARZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
REV. B
–22–
AD7858/AD7858L
Figure 27 shows a system gain calibration (assuming a system
full scale greater than the reference voltage) where the analog
input range has been increased after the system gain calibration
is completed. A system full-scale voltage less than the reference
voltage may also be accounted for by a system gain calibration.
MAX SYSTEM FULL SCALE
IS ⴞ2.5% FROM V
REF
AGND
SYS F.S.
V
REF
– 1LSB
ANALOG
INPUT
RANGE
SYSTEM GAIN
CALIBRATION
MAX SYSTEM FULL SCALE
IS ⴞ2.5% FROM V
REF
AGND
SYS F.S.
V
REF
– 1LSB
ANALOG
INPUT
RANGE
Figure 27. System Gain Calibration
Finally in Figure 28 both the system offset and gain are ac-
counted for by the a system offset followed by a system gain
calibration. First the analog input range is shifted upwards by
the positive system offset and then the analog input range is
adjusted at the top end to account for the system full scale.
MAX SYSTEM OFFSET
IS ⴞ5% OF V
REF
V
REF
–1LSB
SYS OFFSET
AGND
ANALOG
INPUT
RANGE
SYSTEM OFFSET
CALIBRATION
FOLLOWED BY
SYSTEM GAIN
CALIBRATION
MAX SYSTEM OFFSET
IS ⴞ5% OF V
REF
SYS OFFSET
AGND
SYS F.S.
V
REF
– 1LSB
ANALOG
INPUT
RANGE
MAX SYSTEM FULL SCALE
IS ⴞ2.5% FROM V
REF
V
REF
+ SYS OFFSET
MAX SYSTEM FULL SCALE
IS ⴞ2.5% FROM V
REF
SYS F.S.
Figure 28. System (Gain + Offset) Calibration
System Gain and Offset Interaction
The inherent architecture of the AD7858/AD7858L leads to an
interaction between the system offset and gain errors when a
system calibration is performed. Therefore, it is recommended
to perform the cycle of a system offset calibration followed by a
system gain calibration twice. Separate system offset and system
gain calibrations reduce the offset and gain errors to at least the
12-bit level. By performing a system offset CAL first and a
system gain calibration second, priority is given to reducing the
gain error to zero before reducing the offset error to zero. If the
system errors are small, a system offset calibration would be
performed, followed by a system gain calibration. If the system
errors are large (close to the specified limits of the calibration
range), this cycle would be repeated twice to ensure that the
offset and gain errors were reduced to at least the 12-bit level.
The advantage of doing separate system offset and system gain
calibrations is that the user has more control over when the
analog inputs need to be at the required levels, and the
CONVST signal does not have to be used.
Alternatively, a system (gain + offset) calibration can be
performed. It is recommended to perform three system (gain +
offset) calibrations to reduce the offset and gain errors to the
12-bit level. For the system (gain + offset) calibration priority is
given to reducing the offset error to zero before reducing the
gain error to zero. Thus if the system errors are small then two
system (gain + offset) calibrations will be sufficient. If the sys-
tem errors are large (close to the specified limits of the calibra-
tion range) three system (gain + offset) calibrations may be
required to reduced the offset and gain errors to at least the 12-
bit level. There will never be any need to perform more than
three system (offset + gain) calibrations.
The zero scale error is adjusted for an offset calibration and the
positive full-scale error is adjusted for a gain calibration.
System Calibration Timing
The calibration timing diagram in Figure 29 is for a full system
calibration where the falling edge of CAL initiates an internal
reset before starting a calibration (note that if the part is in power-
down mode the CAL pulsewidth must take account of the power-up
time). If a full system calibration is to be performed in software
it is easier to perform separate gain and offset calibrations so
that the CONVST bit in the control register does not have to be
programmed in the middle of the system calibration sequence.
The rising edge of CAL starts calibration of the internal DAC
and causes the BUSY line to go high. If the control register is
set for a full system calibration, the CONVST must be used
also. The full-scale system voltage should be applied to the
analog input pins from the start of calibration. The BUSY line
will go low once the DAC and System Gain Calibration are
complete. Next the system offset voltage is applied to the AIN
pin for a minimum setup time (t
SETUP
) of 100 ns before the
rising edge of the CONVST and remain until the BUSY signal
goes low. The rising edge of the CONVST starts the system
offset calibration section of the full system calibration and also
causes the BUSY signal to go high. The BUSY signal will go
low after a time t
CAL2
when the calibration sequence is com-
plete. In some applications not all the input channels may be
used. In this case it may be useful to dedicate two input chan-
nels for the system calibration, one which has the system offset
voltage applied to it, and one which has the system full scale
voltage applied to it. When a system offset or gain calibration is
performed, the channel selected should correspond to the sys-
tem offset or system full-scale voltage channel.
The timing for a system (gain + offset) calibration is very similar
to that of Figure 29 the only difference being that the time t
CAL1
will be replaced by a shorter time of the order of t
CAL2
as the
internal DAC will not be calibrated. The BUSY signal will
signify when the gain calibration is finished and when the part is
ready for the offset calibration.
t
1
= 100ns MIN,
t
14
= 50/90ns MIN 5V/3V,
t
15
= 2.5 t
CLKIN
MAX,
t
CAL1
= 111114 t
CLKIN
,
t
CAL2
= 13899
t
CLKIN
t
1
t
15
t
CAL1
t
CAL2
t
16
t
SETUP
V
SYSTEM FULL SCALE
V
OFFSET
CAL (I/P)
BUSY (O/P)
CONVST (I/P)
AIN (I/P)
Figure 29. Timing Diagram for Full System Calibration
AD7858/AD7858L
REV. B
–23–
The timing diagram for a system offset or system gain calibra-
tion is shown in Figure 30. Here again the CAL is pulsed and
the rising edge of the CAL initiates the calibration sequence (or
the calibration can be initiated in software by writing to the
control register). The rising edge of the CAL causes the BUSY
line to go high and it will stay high until the calibration se-
quence is finished. The analog input should be set at the correct
level for a minimum setup time (t
SETUP
) of 100 ns before the rising
edge of CAL and stay at the correct level until the BUSY signal
goes low.
CAL (I/P)
BUSY (O/P)
t
1
AIN (I/P)
t
15
t
SETUP
t
CAL2
V
SYSTEM FULL SCALE
OR
V
SYSTEM OFFSET
Figure 30. Timing Diagram for System Gain or System
Offset Calibration
SERIAL INTERFACE SUMMARY
Table IX details the two interface modes and the serial clock
edges from which the data is clocked out by the AD7858/
AD7858L (DOUT Edge) and that the data is latched in on
(DIN Edge).
In both interface Modes 1 and 2 the SYNC is gated with the
SCLK. Thus the SYNC↓ may clock out the MSB of data. Sub-
sequent bits will be clocked out by the Serial Clock, SCLK. The
condition for the SYNC↓ clocking out the MSB of data is as
follows:
The falling edge of SYNC will clock out the MSB if the serial clock
is low when the SYNC goes low.
If this condition is not the case, the SCLK will clock out the
MSB. If a noncontinuous SCLK is used, it should idle high.
Table IX. SCLK Active Edges
Interface Mode
Edge DOUT Edge DIN
1, 2 SCLK↓ SCLK↑
Resetting the Serial Interface
When writing to the part via the DIN line there is the possibility
of writing data into the incorrect registers, such as the test regis-
ter for instance, or writing the incorrect data and corrupting the
serial interface. The SYNC pin acts as a reset. Bringing the
SYNC pin high resets the internal shift register. The first data
bit after the next SYNC falling edge will now be the first bit of a
new 16-bit transfer. It is also possible that the test register con-
tents were altered when the interface was lost. Therefore, once
the serial interface is reset it may be necessary to write the 16-bit
word 0100 0000 0000 0010 to restore the test register to its
default value. Now the part and serial interface are completely
reset. It is always useful to retain the ability to program the
SYNC line from a port of the µController/DSP to have the
ability to reset the serial interface.
Table X summarizes the interface modes provided by the
AD7858/AD7858L. It also outlines the various µP/µC to which
the particular interface is suited.
Interface Mode 1 may only be set by programming the control
register (see section on Control Register).
Some of the more popular µProcessors, µControllers, and the
DSP machines that the AD7858/AD7858L will interface to
directly are mentioned here. This does not cover all µCs, µPs,
and DSPs. A more detailed timing description on each of the
interface modes follows.
Table X. Interface Mode Description
Interface ␮Processor/
Mode ␮Controller Comment
1 8XC51 (2-Wire)
8XL51 (DIN Is an Input/
PIC17C42 Output Pin)
2 68HC11 (3-Wire, SPI)
68L11 (Default Mode)
68HC16
PIC16C64
ADSP21xx
DSP56000
DSP56001
DSP56002
DSP56L002
REV. B
–24–
AD7858/AD7858L
DETAILED TIMING SECTION
Mode 1 (2-Wire 8051 Interface)
The read and writing takes place on the DIN line and the con-
version is initiated by pulsing the CONVST pin (note that in
every write cycle the 2/3 MODE bit must be set to 1). The
conversion may be started by setting the CONVST bit in the
control register to 1 instead of using the CONVST pin.
Below in Figure 31 and in Figure 32 are the timing diagrams for
Operating Mode 1 in Table X where we are in the 2-wire inter-
face mode. Here the DIN pin is used for both input and output
as shown. The SYNC input is level triggered active low and can
be pulsed (Figure 31) or can be constantly low (Figure 32).
In Figure 31 the part samples the input data on the rising edge
of SCLK. After the 16th rising edge of SCLK the DIN is con-
figured as an output. When the SYNC is taken high the DIN is
three-stated. Taking SYNC low disables the three-state on the
DIN pin and the first SCLK falling edge clocks out the first data
bit. Once the 16 clocks have been provided the DIN pin will
automatically revert back to an input after a time, t
14
. Note that
a continuous SCLK shown by the dotted waveform in Figure 35
can be used provided that the SYNC is low for only 16 clock
pulses in each of the read and write cycles.
In Figure 32 the SYNC line is tied low permanently and this
results in a different timing arrangement. With SYNC tied low
permanently the DIN pin will never be three-stated. The 16th
rising edge of SCLK configures the DIN pin as an input or an
output as shown in the diagram. Here no more than 16 SCLK
pulses must occur for each of the read and write operations.
If reading from and writing to the calibration registers in this
interface mode, all the selected calibration registers must be
read from or written to. The read and write operations cannot
be aborted. When reading from the calibration registers, the
DIN pin will remain as an output for the full duration of all the
calibration register read operations. When writing to the calibra-
tion registers, the DIN pin will remain as an input for the full
duration of all the calibration register write operations.
t
3
= –0.4t
SCLK
MIN (NONCONTINUOUS SCLK) ⴞ0.4t
SCLK
ns MIN/MAX (CONTINUOUS SCLK),
t
6
= 75/115ns MAX (5V/3V), t
7
= 40/60ns MIN (5V/3V), t
8
= 20/30ns MIN (5V/3V)
POLARITY PIN LOGIC HIGH
SYNC (I/P)
SCLK (I/P)
DIN (I/O)
t
3
t
11
t
3
t
11
161161
t
12
t
8
t
6
t
6
t
5
t
14
DIN BECOMES AN OUTPUT DIN BECOMES AN INPUT
DB15 DB0 DB15 DB0
THREE-STATE
DATA READDATA WRITE
t
7
Figure 31. Timing Diagram for Read/Write Operation with DIN as an Input/Output
(i.e., Mode 1)
t
6
= 75/115ns MAX (5V/3V), t
7
= 40/60ns MIN (5V/3V), t
8
= 20/30ns MIN (5V/3V),
t
13
= 90/130ns MAX (5V/3V), t
14
= 50/90ns MIN (5V/3V)
POLARITY PIN LOGIC HIGH
SCLK (I/P)
DIN (I/O)
161161
t
13
t
8
t
6
t
6
t
14
DIN BECOMES AN INPUT
DB15 DB0
DB15
DB0
6
t
7
DATA WRITE DATA READ
Figure 32. Timing Diagram for Read/Write Operation with DIN as an Input/Output
and
SYNC
Input Tied Low (i.e., Interface Mode 1)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

AD7858ARZ

Mfr. #:
Buy AD7858ARZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3-5V SGL Supply 200kSPS 8-Ch 12-Bit
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