AD7858/AD7858L
REV. B
–7–
PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Description
1 CONVST Convert Start. Logic Input. A low to high transition on this input puts the track/hold into its hold mode
and starts conversion. When this input is not used, it should be tied to DV
DD
.
2 BUSY Busy Output. The busy output is triggered high by the falling edge of CONVST or rising edge of CAL,
and remains high until conversion is completed. BUSY is also used to indicate when the AD7858/
AD7858L has completed its on-chip calibration sequence.
3 SLEEP Sleep Input/Low-Power Mode. A Logic 0 initiates a sleep, and all circuitry is powered down including the
internal voltage reference provided there is no conversion or calibration being performed. Calibration
data is retained. A Logic 1 results in normal operation. See Power-Down section for more details.
4 REF
IN
/REF
OUT
Reference Input/Output. This pin is connected to the internal reference through a series resistor and is
the reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this
appears at the pin. This pin can be overdriven by an external reference or can be taken as high as AV
DD
.
When this pin is tied to AV
DD,
or when an externally applied reference approaches AV
DD
, the C
REF1
pin
should also be tied to AV
DD
.
5AV
DD
Analog Positive Supply Voltage, +3.0 V to +5.5 V.
6 AGND Analog Ground. Ground reference for track/hold, reference, and DAC.
7C
REF1
Reference Capacitor (0.1 µF Multilayer Ceramic). This external capacitor is used as a charge source for
the internal DAC. The capacitor should be tied between the pin and AGND.
8C
REF2
Reference Capacitor (0.01 µF Ceramic Disc). This external capacitor is used in conjunction with the on-
chip reference. The capacitor should be tied between the pin and AGND.
9–16 AIN1–AIN8 Analog Inputs. Eight analog inputs that can be used as eight single-ended inputs (referenced to AGND)
or four pseudo-differential inputs. Channel configuration is selected by writing to the control register.
Both the positive and negative inputs cannot go below AGND or above AV
DD
at any time. Also the posi-
tive input cannot go below the negative input. See Table III for channel selection.
17 CAL Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A Logic 0 on this pin resets
all calibration control logic and initiates a calibration on its rising edge. There is the option of connecting
a 10 nF capacitor from this pin to DGND to allow for an automatic self-calibration on power-up. This
input overrides all other internal operations. If the autocalibration is not required, this pin should be tied
to a logic high.
18 DV
DD
Digital Supply Voltage, +3.0 V to +5.5 V.
19 DGND Digital Ground. Ground reference point for digital circuitry.
20 DOUT Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.
21 DIN Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can
act as an input pin or as a I/O pin depending on the serial interface mode the part is in (see Table X).
22 CLKIN Master clock signal for the device (4 MHz AD7858, 1.8 MHz AD7858L). Sets the conversion and cali-
bration times.
23 SCLK Serial Port Clock. Logic Input. The user must provide a serial clock on this input.
24 SYNC Frame Sync. Logic Input. This pin is level triggered active low and frames the serial clock for the read
and write operations (see Table IX).
REV. B
–8–
AD7858/AD7858L
TERMINOLOGY
1
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Total Unadjusted Error
This is the deviation of the actual code from the ideal code tak-
ing all errors into account (Gain, Offset, Integral Nonlinearity, and
other errors) at any point along the transfer function.
Unipolar Offset Error
This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB).
Positive Full-Scale Error
This is the deviation of the last code transition from the ideal
AIN(+) voltage (AIN(–) + Full Scale – 1.5 LSB) after the offset
error has been adjusted out.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of crosstalk between
the channels. It is measured by applying a full-scale 25 kHz
signal to the other seven channels and determining how much
that signal is attenuated in the channel of interest. The figure
given is the worst case for all channels.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode and the end of
conversion. Track/hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within ±1/2 LSB, after the end of conversion.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (f
S
/2), excluding dc. The ratio
is dependent on the number of quantization levels in the digitiza-
tion process; the more levels, the smaller the quantization noise.
The theoretical signal to (noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02 N +1.76) dB
Thus for a 12-bit converter, this is 74 dB.
1
AIN(+) refers to the positive input of the pseudo differential pair, and AIN(–)
refers to the negative analog input of the pseudo differential pair or to AGND
depending on the channel configuration.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7858/AD7858L, it is
defined as:
THD dB
()
= 20 log
(V
2
2
+ V
3
2
+ V
4
2
+ V
5
2
+ V
6
2
)
V
1
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
,
and V
6
are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa fb), while the
third order terms include (2fa + fb), (2fa fb), (fa + 2fb), and
(fa 2fb).
Testing is performed using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used. In
this case, the second order terms are usually distanced in fre-
quency from the original sine waves, while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in dBs.
AD7858/AD7858L
REV. B
–9–
ON-CHIP REGISTERS
The AD7858/AD7858L powers up with a set of default conditions. The only writing required is to select the channel configuration.
Without performing any other write operations the AD7858/AD7858L still retains the flexibility for performing a full power-down
and a full self-calibration.
Extra features and flexibility, such as performing different power-down options, different types of calibrations including system
calibration, and software conversion start, can be selected by further writing to the part.
The AD7858/AD7858L contains a Control Register, ADC Output Data Register, Status Register, Test Register, and
10 Calibration Registers. The control register is write-only, the ADC output data register and the status register are read-only, and
the test and calibration registers are both read/write registers. The Test Register is used for testing the part and should not be written to.
Addressing the On-Chip Registers
Writing
A write operation to the AD7858/AD7858L consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine
which register is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are
written that the data is latched into the addressed registers. Table I shows the decoding of the address bits while Figure 4 shows the
overall write register hierarchy.
Table I. Write Register Addressing
ADDR1 ADDR0 Comment
0 0 This combination does not address any register so the subsequent 14 data bits are ignored.
0 1 This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the test
register.
1 0 This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are written
to the selected calibration register.
1 1 This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written to the
control register.
Reading
To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register.
Once the read selection bits are set in the Control Register, all subsequent read operations that follow will be from the selected regis-
ter until the read selection bits are changed in the Control Register.
Table II. Read Register Addressing
RDSLT1 RDSLT0 Comment
0 0 All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-up
default setting. There will always be 4 leading zeros when reading from the ADC Output Data Register.
0 1 All successive read operations will be from TEST REGISTER.
1 0 All successive read operations will be from CALIBRATION REGISTERS.
1 1 All successive read operations will be from STATUS REGISTER.
01 10 11
00 01 10 11
ADDR1, ADDR0
DECODE
TEST
REGISTER
CONTROL
REGISTER
GAIN(1)
OFFSET(1)
DAC(8)
GAIN(1)
OFFSET(1)
OFFSET(1) GAIN(1)
CALIBRATION
REGISTERS
CALSLT1, CALSLT0
DECODE
Figure 4. Write Register Hierarchy/Address Decoding
01 10 11
00 01 10 11
RDSLT1, RDSLT0
DECODE
TEST
REGISTER
STATUS
REGISTER
GAIN(1)
OFFSET(1)
DAC(8)
GAIN(1)
OFFSET(1)
OFFSET(1) GAIN(1)
CALIBRATION
REGISTERS
CALSLT1, CALSLT0
DECODE
00
ADC OUTPUT
DATA REGISTER
Figure 5. Read Register Hierarchy/Address Decoding

AD7858ARZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3-5V SGL Supply 200kSPS 8-Ch 12-Bit
Lifecycle:
New from this manufacturer.
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