AD7858/AD7858L
REV. B
–25–
Mode 2 (3-Wire SPI/QSPI Interface Mode)
This is the DEFAULT INTERFACE MODE.
In Figure 33 below we have the timing diagram for interface
Mode 2 which is the SPI/QSPI interface mode. Here the SYNC
input is active low and may be pulsed or tied permanently low.
If SYNC is permanently low, 16 clock pulses must be applied to
the SCLK pin for the part to operate correctly, otherwise with a
pulsed SYNC input a continuous SCLK may be applied pro-
vided SYNC is low for only 16 SCLK cycles. In Figure 33 the
SYNC going low disables the three-state on the DOUT pin.
The first falling edge of the SCLK after the SYNC going low
clocks out the first leading zero on the DOUT pin. The DOUT
pin is three-stated again a time t
12
after the SYNC goes high.
With the DIN pin the data input has to be set up a time t
7
be-
fore the SCLK rising edge as the part samples the input data on
the SCLK rising edge in this case. If resetting the interface is
required, the SYNC must be taken high and then low.
t
11
t
12
16654321
t
10
t
8
t
6
t
9
t
8
t
6
t
3
t
5
THREE-STATE THREE-STATE
DB0DB10DB11DB12DB13DB14
DB15 DB14 DB13 DB12 DB11 DB10 DB0
SYNC (I/P)
SCLK (I/P)
DOUT (O/P)
DIN (I/P)
POLARITY PIN LOGIC HIGH
t
3
= 0.4t
SCLK
MIN (NONCONTINUOUS SCLK) 0.4t
SCLK
ns MIN/MAX (CONTINUOUS SCLK),
t
6
= 75/115ns MAX (5V/3V), t
7
= 40/60ns MIN (5V/3V), t
8
= 20/30ns MIN (5V/3V),
t
11
= 30/50ns MIN (NONCONTINUOUS SCLK) (5V/3V), (30/50)/0.4t
SCLK
ns MIN/MAX
(CONTINUOUS SCLK) (5V/3V)
DB15
t
7
Figure 33. SPI/QSPI Mode 2 Timing Diagram for Read/Write Operation
with DIN Input, DOUT Output, and
SYNC
Input
REV. B
–26–
AD7858/AD7858L
CONFIGURING THE AD7858/AD7858L
The AD7858/AD7858L contains 14 on-chip registers which can
be accessed via the serial interface. In the majority of applications it
will not be necessary to access all of these registers. Here the
CLKIN signal is applied directly after power-on; the CLKIN
signal must be present to allow the part to perform a calibration.
This automatic calibration will be completed approximately 32 ms
after the AD7858 has powered up (4 MHz CLK).
For accessing the on-chip registers it is necessary to write to the
part. To change the channel from the default channel setting
the user will be required to write to the part. To enable Serial
Interface Mode 1 the user must also write to the part. Figure 34
and 35 outline flowcharts of how to configure the AD7858/
AD7858L Serial Interface Modes 1 and 2 respectively. The
continuous loops on all diagrams indicate the sequence for more
than one conversion. The options of using a hardware (pulsing
the CONVST pin) or software (setting the CONVST bit to 1)
conversion start, and reading/writing during or after conversion
are shown in Figures 34 and 35. If the CONVST pin is never
used then it should be tied to DV
DD
permanently. Where refer-
ence is made to the BUSY bit equal to a Logic 0, to indicate the
end of conversion, the user in this case would poll the BUSY bit
in the status register.
Interface Mode 1 Configuration
Figure 34 shows the flowchart for configuring the part in Inter-
face Mode 1. This mode of operation can only be enabled by
writing to the control register and setting the 2/3 MODE bit.
Reading and writing cannot take place simultaneously in this
mode as the DIN pin is used for both reading and writing.
INITIATE
CONVERSION
IN
SOFTWARE
?
START
POWER-ON, APPLY CLKIN SIGNAL,
WAIT FOR AUTOMATIC CALIBRATION
APPLY SYNC (IF REQUIRED), SCLK,
WRITE TO CONTROL REGISTER
SETTING CHANNEL AND TWO-WIRE MODE
PULSE CONVST PIN
WAIT FOR BUSY SIGNAL TO GO LOW
OR
WAIT FOR BUSY BIT = 0
NO
1
SERIAL
INTERFACE
MODE
?
APPLY SYNC (IF REQUIRED), SCLK, WRITE
TO CONTROL REGISTER SETTING CHANNEL
TWO-WIRE MODE
READ
DATA
DURING
CONVERSION
?
NO
YES
YES
APPLY SYNC (IF REQUIRED), SCLK, READ
CURRENT CONVERSION RESULT ON DIN PIN
APPLY SYNC (IF REQUIRED), SCLK, READ
PREVIOUS CONVERSION RESULT ON DIN PIN
WAIT APPROX. 200ns AFTER
CONVST RISING EDGE OR AFTER END
OF CONTROL REGISTER WRITE
WRITE
TO CONTROL REGISTER SETTING CONVST
BIT TO 1 (SEE NOTE)
NOTE:
TWO SEPARATE WRITES ARE REQUIRED TO SET A NEW CHANNEL ADDRESS AND INITIATE A
CONVERSION ON THAT NEW CHANNEL IN SOFTWARE AS THE ACQUISITION TIME (2
t
CLKIN
)
MUST ELAPSE BEFORE THE CONVERSION BEGINS. IF BOTH COMMANDS ARE ISSUED IN THE ONE
WRITE THE RESULT OF THIS CONVERSION SHOULD BE DISCARDED AND THE NEXT
CONVERSION ON THAT SAME CHANNEL WILL PROVIDE CORRECT RESULTS.
Figure 34. Flowchart for Setting Up, Reading, and Writing in Interface Mode 1
AD7858/AD7858L
REV. B
–27–
Interface Mode 2 Configuration
Figure 35 shows the flowchart for configuring the part in Inter-
face Mode 2. In this case the read and write operations take
place simultaneously via the serial port. Writing all 0s ensures
that no valid data is written to any of the registers. When using
the software conversion start and transferring data during con-
version Note 1 must be obeyed.
APPLY SYNC (IF REQUIRED), SCLK, WRITE
TO CONTROL REGISTER SETTING CHANNEL,
(SEE NOTE 1)
INITIATE
CONVERSION
IN
SOFTWARE
?
START
POWER-ON, APPLY CLKIN SIGNAL,
WAIT FOR AUTOMATIC CALIBRATION
PULSE CONVST PIN
WAIT FOR BUSY SIGNAL TO GO LOW
OR
WAIT FOR BUSY BIT = 0
NO
SERIAL
INTERFACE
MODE
?
TRANSFER
DATA DURING
CONVERSION
?
NO
YES
YES
APPLY SYNC (IF REQUIRED), SCLK,
READ CURRENT CONVERSION RESULT
ON DOUT PIN, AND WRITE CHANNEL
SELECTION
NOTES
1
WHEN USING THE SOFTWARE CONVERSION START AND TRANSFERRING DATA DURING CONVERSION THE USER MUST ENSURE THE CONTROL REGISTER
WRITE OPERATION EXTENDS BEYOND THE FALLING EDGE OF BUSY. THE FALLING EDGE OF BUSY RESETS THE CONVST BIT TO 0 AND ONLY AFTER THIS
TIME CAN IT BE REPROGRAMMED TO 1 TO START THE NEXT CONVERSION.
2
TWO SEPARATE WRITES ARE REQUIRED TO SET A NEW CHANNEL ADDRESS AND INITIATE A CONVERSION ON THAT NEW CHANNEL IN SOFTWARE AS
THE ACQUISITION TIME (2
t
CLKIN
) MUST ELAPSE BEFORE THE CONVERSION BEGINS. IF BOTH COMMANDS ARE ISSUED IN THE ONE WRITE THE
RESULT OF THIS CONVERSION SHOULD BE DISCARDED AND THE NEXT CONVERSION ON THAT SAME CHANNEL WILL PROVIDE CORRECT RESULTS.
WAIT APPROX 200ns AFTER
CONVST RISING EDGE
APPLY SYNC (IF REQUIRED), SCLK, READ
PREVIOUS CONVERSION RESULT ON DOUT
PIN, AND WRITE CHANNEL SELECTION
NO
APPLY SYNC (IF REQUIRED), SCLK, WRITE
TO CONTROL REGISTER SETTING CHANNEL
WAIT FOR BUSY SIGNAL TO GO LOW
OR
WAIT FOR BUSY BIT = 0
YES
2
WRITE TO CONTROL REGISTER SETTING
CONVST BIT TO 1, READ
CURRENT CONVERSION RESULT
ON DOUT PIN (SEE NOTE 2)
WRITE TO CONTROL REGISTER
SETTING CONVST BIT TO 1,
READ PREVIOUS RESULT ON
DOUT PIN (SEE NOTES 1&2)
TRANSFER
DATA DURING
CONVERSION
?
Figure 35. Flowchart for Setting Up, Reading, and Writing in Interface Mode 2

AD7858ARZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3-5V SGL Supply 200kSPS 8-Ch 12-Bit
Lifecycle:
New from this manufacturer.
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