3
FN8112.1
May 17, 2006
Low V
CC
detection circuitry protects the user’s system
from low voltage conditions, resetting the system
when V
CC
falls below the minimum V
TRIP1
point.
RESET/RESET
is active until V
CC
returns to proper
operating level and stabilizes. A second voltage moni-
tor circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available. However, Intersil’s unique circuits allows the
threshold for either voltage monitor to be repro-
grammed to meet specific system level requirements
or to fine-tune the threshold for applications requiring
higher precision.
A manual reset input provides debounce circuitry for
minimum reset component count.
A battery switch circuit compares V
CC
with V
BATT
input
and connects V
OUT
to whichever is higher. This pro-
vides voltage to external SRAM or other circuits in the
event of main power failure. The X40020/21 can drive
50mA from V
CC
to 250µA from V
BATT
. The device only
switches to V
BATT
when V
CC
drops below the low V
CC
voltage threshold and V
BATT
.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO
signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The device features an 2-wire interface and software
protocol allowing operation on a two-wire bus.
The device utilizes Intersil’s proprietary Direct Write
™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
PIN CONFIGURATION
V
BATT
V
SS
V
CC
SDA
SCL
3
2
4
1
12
13
11
14
LOWLINE
WDO
RESET
7
6
5
8
9
10
V2MON
MR
WP
3
2
4
1
12
13
11
14
7
6
5
8
9
10
V
OUT
BATT-ON
V2FAIL
V
BATT
V
CC
SDA
SCL
WP
V
OUT
BATT-ON
V
SS
LOWLINE
WDO
RESET
V2MON
MR
V2FAIL
X40020
X40021
14-Pin SOIC, TSSOP
14-Pin SOIC, TSSOP
PIN DESCRIPTION
Pin Name Function
1V2FAILV2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V
TRIP2
and
goes HIGH when V2MON exceeds V
TRIP2
. There is no power-up reset delay circuitry on this pin.
2V2MONV2 Voltage Monitor Input. When the V2MON input is less than the V
TRIP2
voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V
SS
or V
CC
when
not used.
3LOWLINE
Early Low V
CC
Detect. This open drain output signal goes LOW when V
CC
< V
TRIP1
.
When
V
CC
> V
TRIP1
, this pin is pulled high with the use of an external pull up resistor.
4WDOWDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
5MR
Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will
remain HIGH/LOW until the pin is released and for the t
PURST
thereafter. It has an internal pull up
resistor.
6 RESET
/
RESET
RESET Output. (X40021) This open drain pin is an active LOW output which goes LOW whenever
V
CC
falls below V
TRIP1
voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t
PURST
) on power-up. It will also stay active until manual reset is released and
for t
PURST
thereafter.
RESET Output. (X40020) This pin is an active HIGH open drain output which goes HIGH whenever
V
CC
falls below V
TRIP1
voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t
PURST
) on power-up. It will also stay active until manual reset is released and
for t
PURST
thereafter.
X40020, 40021
