16
FN8112.1
May 17, 2006
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or t
WC
after a stop ending a write operation.
(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; t
WC
after a stop that initiates a
high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) Negative numbers indicate charging current, positive numbers indicate discharge current.
(4) V
IL
Min. and V
IH
Max. are for reference only and are not tested.
(5) At 25°C, V
CC
= 3V.
(6) See ordering information for standard programming levels. For custom programming levels, contact factory.
(7) Based on characterization data.
EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2)
V
HYS
(7)
Schmitt Trigger Input Hysteresis
• Fixed input level
V
CC
related level
0.2
.05 x V
CC
V
V
V
OL
Output LOW Voltage (SDA, RESET/RE-
SET, LOWLINE, V2FAIL, WDO)
0.4 V I
OL
= 3.0mA (2.7-5.5V)
I
OL
= 1.8mA (2.4-3.6V)
V
CC
Supply
V
TRIP1
(6)
V
CC
Reset Trip Point Voltage Range 2.0 4.75 V
4.55 4.6 4.65 A, B Version
2.85 2.9 2.95 C Version
t
RPDL
(7)
V
TRIP
1
to LOWLINE
S
Second Supply Monitor
V
TRIP2
(6)
V2MON Reset Trip Point Voltage Range 0.9 3.5 V
2.85 2.9 2.95 A Version
2.55 2.6 2.65 B Version
1.55 1.6 1.65 C Version
t
RPD2
(7)
V
TRIP
2
to V2FAIL
S
D.C. OPERATING CHARACTERISTICS (Continued)
(Over the recommended operating conditions unless otherwise specified)
Symbol Parameter Min. Typ.
(5)
Max. Unit Test Conditions
+
V
REF
t
RPDX
= 5µs worst case
Output
VxMON
R
C
V = 100mV
V
V
REF
X40020, 40021
17
FN8112.1
May 17, 2006
CAPACITANCE
Note: (1) This parameter is not 100% tested.
EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR
V
CC
= 5V
A.C. TEST CONDITIONS
SYMBOL TABLE
Symbol Parameter Max. Unit Test Conditions
C
OUT
(1)
Output Capacitance (SDA, RESET, RESET/LOWLINE,
V2FAIL
, WDO)
8pF V
OUT
= 0V
C
IN
(1)
Input Capacitance (SCL, WP) 6 pF V
IN
= 0V
Input pulse levels V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times 10ns
Input and output timing levels
V
CC
x 0.5
Output load Standard output load
5V
SDA
30pF
V2MON
4.6k
RESET
30pF
2.06k
V2FAIL
V
OUT
4.6k
30pF
WDO/LOWLINE
Must be
steady
Will be
steady
May change
from LOW
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
WAVEFORM INPUTS OUTPUTS
X40020, 40021
18
FN8112.1
May 17, 2006
A.C. CHARACTERISTICS
Note: (1) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
Symbol Parameter
400kHz
UnitMin. Max.
f
SCL
SCL Clock Frequency 400 kHz
t
IN
Pulse width Suppression Time at inputs 50 ns
t
AA
SCL LOW to SDA Data Out Valid 0.1 0.9 µs
t
BUF
Time the bus free before start of new transmission 1.3 µs
t
LOW
Clock LOW Time 1.3 µs
t
HIGH
Clock HIGH Time 0.6 µs
t
SU:STA
Start Condition Setup Time 0.6 µs
t
HD:STA
Start Condition Hold Time 0.6 µs
t
SU:DAT
Data In Setup Time 100 ns
t
HD:DAT
Data In Hold Time 0 µs
t
SU:STO
Stop Condition Setup Time 0.6 µs
t
DH
Data Output Hold Time 50 ns
t
R
SDA and SCL Rise Time 20 +.1Cb
(1)
300 ns
t
F
SDA and SCL Fall Time 20 +.1Cb
(1)
300 ns
t
SU:WP
WP Setup Time 0.6 µs
t
HD:WP
WP Hold Time 0 µs
Cb Capacitive load for each bus line 400 pF
t
SU:STO
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA IN
SDA OUT
t
F
t
LOW
t
BUF
t
R
t
DH
t
AA
X40020, 40021

X40020S14IZ-AT1

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Supervisory Circuits DL VAGE CPU SUPS HI IND VTRIP1 4 6
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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