19
FN8112.1
May 17, 2006
WP Pin Timing
Write Cycle Timing
Nonvolatile Write Cycle Timing
Note: (1) t
WC
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Power Fail Timings
Symbol Parameter Min. Typ.
(1)
Max. Unit
t
WC
(1)
Write Cycle Time 5 10 ms
t
HD:WP
SCL
SDA IN
WP
t
SU:WP
Clk 1 Clk 9
Slave Address Byte
START
SCL
SDA
t
WC
8
th
Bit of Last Byte
ACK
Stop
Condition
Start
Condition
V2MON
V2FAIL
t
R
t
F
t
RPDX
V
RVALID
LOWLINE or
V
CC
or
V
TRIPX
t
RPDX
t
RPDX
t
RPDL
t
RPDL
t
RPDL
X = 1, 2
X40020, 40021
20
FN8112.1
May 17, 2006
RESET/RESET/MR Timings
LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, VCC = 5V)
Note: (1) Based on characterization data.
Symbol Parameters Min. Typ. Max. Unit
t
RPD1
(1)
t
RPDL
V
TRIP1
to RESET/RESET (Power-down only)
V
TRIP1
to LOWLINE
s
t
LR
(1)
LOWLINE to RESET/RESET delay (Power-down only) [= t
RPD1
-t
RPDL
] 500 ns
t
RPD2
(1)
V
TRIP2
to V2FAIL s
t
PURST
Power-on Reset delay:
PUP1 = 0, PUP0 = 0
PUP1 = 0, PUP0 = 1 (Factory default)
PUP1 = 1, PUP0 = 0
PUP1 = 1, PUP0 = 1
50
(1)
200
400
(1)
800
(1)
ms
ms
ms
ms
t
F
V
CC,
V2MON
Fall Time 20 mVµs
t
R
V
CC,
V2MON
Rise Time 20 mVµs
V
RVALID
Reset Valid V
CC
1V
t
MD
(1)
MR to RESET/ RESET delay (activation only) 500 ns
t
in1
Pulse width Suppression Time for MR 50ns
t
WDO
Watchdog Timer Period:
WD1 = 0, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 1, WD0 = 0
WD1 = 1, WD0 = 1 (factory default)
1.4
(1)
200
(1)
25
OFF
s
ms
ms
t
RST1
Watchdog Reset Time Out Delay
WD1 = 0, WD0 = 0
WD1 = 0, WD0 = 1
100 200 300 ms
t
RST2
Watchdog Reset Time Out Delay WD1=1, WD0=0 12.5 25 37.5 ms
t
RSP
Watchdog timer restart pulse width 1 µs
V
CC
V
TRIP1
RESET
RESET
t
PURST
t
PURST
t
R
t
F
t
RPD1
V
RVALID
MR
t
MD
X40020, 40021
21
FN8112.1
May 17, 2006
Watchdog Time Out For 2-Wire Interface
V
TRIPX
Set/Reset Conditions
< t
WDO
t
RST
WDO
SDA
Start
t
WDO
t
RST
SCL
Start
t
RSP
WDT
Restart
Start
SDA
SCL
Minimum Sequence to Reset WDT
Clockin (0 or 1)
SCL
SDA
V
CC
/V2MON
(V
TRIPX
)
WDO
t
TSU
t
THD
t
VPH
t
VPS
V
P
t
WC
t
VPO
A0h
0
7
70 7
sets V
TRIP1
sets V
TRIP2
*01h
*09h
*03h
*0Bh
resets V
TRIP2
resets V
TRIP1
0
Start
* all others reserved
00h
*
X40020, 40021

X40020S14IZ-AT1

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Supervisory Circuits DL VAGE CPU SUPS HI IND VTRIP1 4 6
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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