13
FN8112.1
May 17, 2006
Read Operation
Prior to issuing the Slave Address Byte with the R/W
bit
set to one, the master must first perform a “dummy” write
operation. The master issues the start condition and the
Slave Address Byte, receives an acknowledge, then
issues the Word Address Bytes. After acknowledging
receipts of the Word Address Bytes, the master immedi-
ately issues another start condition and the Slave
Address Byte with the R/W
bit set to one. This is followed
by an acknowledge from the device and then by the eight
bit word. The master terminates the read operation by
not responding with an acknowledge and then issuing a
stop condition. See Figure 12 for the address, acknowl-
edge, and data transfer sequence.
SERIAL DEVICE ADDRESSING
Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FF
hex
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FF
hex
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
a device type identifier that is always “1011” when
accessing the control register and fault detection
register.
two bits of “0”.
one bit that becomes the MSB of the memory
address X
4
.
last bit of the slave command byte is a R/W
bit. The
R/W
bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W
bit is a one,
then a read operation is selected. A zero selects a
write operation. See Figure 13.
Figure 12. Read Sequence
0
Slave
Address
Byte
Address
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
1
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master
101
0
01
11111111
X40020, 40021
14
FN8112.1
May 17, 2006
Figure 13. Slave Address, Word Address, and Data Bytes
Word Address
The word address is either supplied by the master or
obtained from an internal counter.
Operational Notes
The device powers-up in the following state:
The device is in the low power standby state.
The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
SDA pin is the input mode.
RESET/RESET
Signal is active for t
PURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
The WEL bit must be set to allow write operations.
The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
The WP pin, when held HIGH, prevents all writes to
the array and all the Register.
General Purpose Memory
Control Register
Fault Detection Register
1
1
0
0
1
1
0
1
A8
R/W
Word Address
Slave Byte
1
0
1011
0
0
0
0
0
0
R/W
R/W
General Purpose Memory
Control Register
Fault Detection Register
A7
1
A6 A5 A4
A1
A0
1
A3 A2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X40020, 40021
15
FN8112.1
May 17, 2006
ABSOLUTE MAXIMUM RATINGS
Temperature under bias .................... -65°C to +135°C
Storage temperature.......................... -65°C to +150°C
Voltage on any pin with
respect to V
SS
...................................... -1.0V to +7V
D.C. output current ...............................................5mA
Lead temperature (soldering, 10s) .................... 300°C
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
*See Ordering Info
Temperature Min. Max.
Commercial 0°C 70°C
Industrial -40°C +85°C
Version Chip Supply Voltage
Monitored
Voltages*
-A or -B 2.7V to 5.5V 2.6 to 5.5V
-C 2.7V to 5.5V 1.6V to 3.6V
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified)
Symbol Parameter Min. Typ.
(5)
Max. Unit Test Conditions
I
CC1
(1)
Active Supply Current (V
CC
) Read
(Excludes I
OUT
)
1.5 mA V
IL
= V
CC
x 0.1
V
IH
= V
CC
x 0.9,
f
SCL
= 400kHz
I
CC2
(1)
Active Supply Current (V
CC
) Write Non
Volatile Memory (Excludes I
OUT
)
3.0 mA
I
SB1
(1)(7)
Standby Current (V
CC
) AC (WDT off) 6 10 µA V
IL
= V
CC
x 0.1
VIH =
V
CC
x 0.9
f
SCL
, f
SDA
= 400kHz
I
SB2
(2)(7)
Standby Current (V
CC
) DC (WDT on) 25 30 µA V
SDA
= V
SCL
= V
CC
Others = GND or V
CC
I
BATT1
(3)(7
)
V
BATT
Current (Excludes I
OUT
)0.21µAV
OUT
= V
CC
I
BATT2
(7)
V
BATT
Current (Excludes I
OUT
)
(Battery Backup Mode)
0.2 6 µA V
BATT
= 2.8V
V
OUT
= Open
V
OUT1
(7)
Output Voltage (V
CC
> V
BATT
+ 0.03V
or V
CC
> V
TRIP1
)
V
CC
-0.05V
V
CC
-0.5V
VI
OUT
= 5mA V
CC
= (4.5-5.5V)
I
OUT
= 50mA V
CC
= (4.5-5.5V)
V
OUT2
(7)
Output Voltage (V
CC
< V
BATT
- 0.03V
and V
CC
< V
TRIP1
) {Battery Backup}
V
BATT
-0.2 V I
OUT
= 250µA
V
OLB
Output (BATT-ON) LOW Voltage 0.4 V I
OL
= 3.0mA (4.5-5.5V)
V
OHB
Output (BATT-ON) HIGH Voltage V
OUT
-0.8 V I
OH
= -0.4mA (4.5-5.5V)
V
BSH
(7)
Battery Switch Hysteresis
(V
CC
< V
TRIP1
)
30
-30
mV Power-up
Power-down
I
LI
Input Leakage Current (SCL, MR,WP) 10 µA V
IL
= GND to V
CC
I
LO
Output Leakage Current (SDA, V2FAIL,
WDO
, RESET)
10 µA V
SDA
= GND to V
CC
Device is in Standby
(2)
V
IL
(3)
Input LOW Voltage (SDA, SCL, MR,WP) -0.5 V
CC
x 0.3 V
V
IH
(3)
Input HIGH Voltage (SDA, SCL, MR,WP) V
CC
x 0.7 V
CC
+ 0.5 V
X40020, 40021

X40020S14IZ-AT1

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Supervisory Circuits DL VAGE CPU SUPS HI IND VTRIP1 4 6
Lifecycle:
New from this manufacturer.
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