KS8721CL Micrel, Inc.
M9999-041405 16 April 2005
Power Management
The KS8721CL offers the following modes for power management:
Power-Down Mode: This mode can be achieved by writing to Register 0.11 or pulling pin 30 PD# low.
Power-Saving Mode: This mode can be disabled by writing to Register 1fh.10. The KS8721CL turns off everything
except for the Energy Detect and PLL circuits when the cable is not installed. In other words, the KS8721CL shuts
down most of the internal circuits to save power if there is no link. Power-saving mode is in the most effective state
when auto-negotiation mode is enabled.
100BT FX Mode
Please contact your local field application engineer (FAE) for a reference schematic on fiber connection.
100BT FX mode is activated when FXSD/FXEN is higher than 0.6V (this pin has a default pull down). Under this mode, the
auto-negotiation and auto-MDI-X features are disabled.
In fiber operation, the FXSD pin should connect to the signal detect (SD) output of the fiber module. The internal threshold of
FXSD is around 1/2 V
DD
±50mV (1.25V ±0.05V). Above this level, the fiber signal is considered detected. The operation is
summarized in the following table:
FXSD/FXEN Condition
Less than 0.6V 100TX mode
Less than 1.25V, FX mode
but greater than 0.6V No signal detected
FEF generated
Greater than 1.25 FX mode
Signal detected
Table 1. 100BT FX Mode
To ensure proper operation, the swing of fiber module SD should cover the threshold variation. A resistive voltage divider is
recommended to adjust the SD voltage range.
FEF, repetition of a special pattern which consists of 84-one and 1-zero, is generated under “FX mode with no signal detected.”
The purpose of FEF is to notify the sender of a faulty link. When receiving an FEF, the LINK will go down to indicate a fault,
even with fiber signal detected. The transmitter is not affected by receiving an FEF and still sends out its normal transmit pattern
from MAC. FEF can be disabled by strapping pin 27 low. Refer to the “Strapping Options” section.
Media Converter Operation
The KS8721CL is capable of performing media conversion with two parts in a back-to-back RMII loop-back mode as indicated
in the diagram. Both parts are in RMII mode and with RMII BTB asserted (pins 21 and 22 strapped high). One part is operating
in TX mode and the other is operating in FX mode. Both parts can share a common 50MHz oscillator.
Under this operation, auto-negotiation on the TX side prohibits 10BASE-T link-up. Additional options can be implemented
under this operation. Disable the transmitter and set it at tri-state by controlling the high TXD2 pin. In order to do this, RXD2
and TXD2 pins need to be connected via inverter. When TXD2 pin is high in both the copper and fiber operation, it is disabled
transmit. Meanwhile, the RXD2 pin on the copper side serves as the energy detect and can indicate if a line signal is detected.
TXD3 should be tied low and RXD3 allowed to float. Please contact your Micrel FAE for a media converter reference design.
Figure 3. Fiber Module
Rx
+/-
Tx +/-
FTx
FR
x
Pin
34
TxD
(Fiber Mode)
21 22
Pin
Pin
21 22
50MHz
V
CC
OSC
TxC/
Ref_CLK
TxC/
Ref_CLK
RxD
RxD
V
CC
KS8721CL
KS8721CL
To the SD Pin of the
Fiber Module
TxD
April 2005 17 M9999-041405
KS8721CL Micrel, Inc.
Circuit Design Reference for Power Supply
Micrel’s integrated built-in, voltage regulator technology allows the user to save BOM costs on both existing and future designs
with the use of the new KS8721CL single supply, single port, 10/100 Ethernet PHY.
7
24
+3.3V
KS8721CL
812233536394344
VDDI/O
VDDI/O
VDDC VDDPLL
Voltag e
Regulator
10µF
+2.5V +2.5VPLL
Ferrite Bead
10µF
10µF 10µF
13 47
+2.5VA
Ferrite Bead
VDDTX
OUTIN
GND
42 31 38
10µF 10µ
F
VDDRX
VDDRCV
Figure 4. Circuit Design
The circuit design in Figure 4 shows the power connections for the power supply: the 3.3V to VDDI/O is the only input power
source and the 2.5V at VDDRCV, pin 38, is the output of the voltage regulator that needs to supply through the rest of the 2.5V
VDD pins via the 2.5V power plane.
KS8721CL Micrel, Inc.
M9999-041405 18 April 2005
Address Name Description Mode
(1)
Default
Register 0h - Basic Control
0.15 Reset 1 = software reset. Bit is self-clearing. RW/SC 0
0.14 Loop-Back 1 = loop-back mode; 0 = normal operation. RW 0
0.13 Speed Select (LSB) 1 = 100Mbps; 0 = 10Mbps. RW Set by
Ignored if Auto-Negotiation is enabled (0.12 = 1). SPD100
0.12 Auto-Negotiation Enable 1 = enable auto-negotiation process (override 0.13 and 0.8). RW Set by
0 = disable auto-negotiation process. NWAYEN
0.11 Power Down 1 = power-down mode; 0 = normal operation. RW 0
0.10 Isolate 1 = electrical isolation of PHY from MII and TX+/TX-. RW Set by ISO
0 = normal operation.
0.9 Restart Auto-Negotiation 1 = restart auto-negotiation process. RW/SC 0
0 = normal operation. Bit is self-clearing.
0.8 Duplex Mode 1 = full-duplex; 0 = half-duplex. RW Set by
DUPLEX
0.7 Collision Test 1 = enable COL test; 0 = disable COL test. RW 0
0.6:1 Reserved RO 0
0.0 Disable 0 = enable transmitter. R/W 0
Transmitter 1 = disable transmitter.
Register 1h - Basic Status
1.15 100BASE-T4 1 = T4 capable; 0 = not T4 capable. RO 0
1.14 100BASE-TX Full-Duplex 1 = capable of 100BASE-X full-duplex. RO 1
0 = not capable of 100BASE-X full-duplex.
1.13 100BASE-TX Half-Duplex 1 = capable of 100BASE-X half-duplex. RO 1
0 = not capable of 100BASE-X half-duplex.
1.12 10BASE-T Full-Duplex 1 = 10Mbps with full-duplex. RO 1
0 = no 10Mbps with full-duplex capability.
1.11 10BASE-T Half-Duplex 1 = 10Mbps with half-duplex. RO 1
0 = no 10Mbps with half-duplex capability.
Note:
1. RW: Read/Write, RO: Read Only, SC: Self Clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See “Strapping
Options.”
Register Map
Register No. Description
0h Basic Control Register
1h Basic Status Register
2h PHY Identifier I
3h PHY Identifier II
4h Auto-Negotiation Advertisement Register
5h Auto-Negotiation Link Partner Ability Register
6h Auto-Negotiation Expansion Register
7h Auto-Negotiation Next Page Register
8h Link Partner Next Page Ability
15h RXER Counter Register
1bh Interrupt Control/Status Register
1fh 100BASE-TX PHY Control Register

KSZ8721CL-TR

Mfr. #:
Manufacturer:
Microchip Technology / Micrel
Description:
Ethernet ICs 10/100 BASE-TX/FX Physical Layer Transceiver
Lifecycle:
New from this manufacturer.
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