KS8721CL Micrel, Inc.
M9999-041405 30 April 2005
tsr
Supply
Voltage
RST_N
Strap-In
Value
Figure 10. Reset Timing
Symbol Parameter Min Typ Max Units
t
sr
Stable Supply Voltages to Reset High 50 µs
Table 7. Reset Timing Parameters
Reset Circuit Diagram
Micrel recommendeds the following discrete reset circuit as shown in Figure 11 when powering up the KS8721CL device. For
the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the reset circuit
as shown in Figure 12.
VCC
R
10k
D2
C
10µF
D1
CPU/FPGA
RST_OUT_n
KS8721CL
RST
D1, D2: 1N4148
Figure 11. Recommended Reset Circuit.
VCC
R
10k
C
10µF
D1
KS8721CL
RST
D1: 1N4148
Figure 12. Recommended Circuit for Interfacing with CPU/FPGA Reset
At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out from CPU/FPGA
provides warm reset after power up. It is also recommended to power up the VDD core voltage earlier than VDDIO voltage.
At worst case, the both VDD core and VDDIO voltages should come up at the same time.
Reference Circuit for Strapping Option Configuration
Figure 10 shows the reference circuit for strapping option pins.
