April 2005 25 M9999-041405
KS8721CL Micrel, Inc.
Timing Diagrams
T
X
C
t
H
D
2
t
S
U
2
T
X
E
N
T
X
D
[
3
:0
]
t
S
U
1
t
H
D
1
C
R
S
t
C
R
S
2
t
C
R
S
1
T
X
P
/
T
XM
t
L
A
T
V
a
l
i
d
D
a
t
a
T
X
C
t
S
Q
E
C
O
L
t
S
Q
E
P
SQ
E
T
i
m
i
n
g
T
X
E
N
Figure 5. 10BASE-T MII Transmit Timing
Symbol Parameter Min Typ Max Units
t
SU1
TXD [3:0] Set-Up to TXC High 10 ns
t
SU2
TXEN Set-Up to TXC High 10 ns
t
HD1
TXD [3:0] Hold After TXC High 0 ns
t
HD2
TXEN Hold After TXC High 0 ns
t
CRS1
TXEN High to CRS Asserted Latency 4 BT
(1)
t
CRS2
TXEN Low to CRS De-Asserted Latency 8 BT
t
LAT
TXEN High to TXP/TXM Output (TX Latency) 4 BT
t
SQE
COL (SQE) Delay After TXEN De-Asserted 2.5 µs
t
SQEP
COL (SQE) Pulse Duration 1.0 µs
Table 2. 10BASE-T MII Transmit Timing Parameters
Note:
1. BT = bit time.
1BT = 10ns @ 100BT.
