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KSZ8721CL-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
April 2005 7 M9999-041405
KS8721CL Micrel, Inc.
Pin Number Pin Name Type
(1)
Pin Function
19 TXD2 Ipd MII Transmit Data Input.
20 TXD3 Ipd MII Transmit Data Input.
21 COL/RMII Ipd/O MII Collision Detect Output.
During reset, the pull-up/pull-down value is latched as RMII select. See “Strapping
Options” section for details.
22 CRS/ Ipd/O MII Carrier Sense Output.
RMII_BTB During reset, the pull-up/pull-down value is latched as RMII back-to-back mode
when RMII mode is selected. See “Strapping Options” section for details.
23 GND GND Ground.
24 VDDIO P Digital IO 2.5/3.3V tolerant power supply. 3.3V power input of voltage regulator.
See “Circuit Design Ref. for Power Supply” section for details.
25 INT#/ Ipu/O Management Interface (MII) Interrupt Out. Interrupt level set by
PHYAD0 Register 1f, bit 9.
During reset, latched as PHYAD[0]. See “Strapping Options” section for details.
26 LED0/TEST Ipu/O Link LED Output. The external pull-down enable test mode and only used
PHYAD0 for the factory test. Active low.
Link Pin State LED Definition
No Link H “Off”
Link L “On”
27 LED1/ Ipu/O Speed LED Output. Latched as SPEED (Register 0, bit 13) during power-up/
SPD100/ reset. See “Strapping Options” section for details. Active low.
nFEF
Speed Pin State LED Definition
10BT H “Off”
100BT L “On”
28 LED2/ Ipu/O Full-duplex LED Output. Latched as DUPLEX (register 0h, bit 8) during power-up/
reset. See “Strapping DUPLEX Options” section for details. Active low.
Duplex Pin State LED Definition
Half H “Off”
Full L “On”
29 LED3/ Ipu/O LED Output. Latched as ANEG_EN (register 0h, bit 12) during power-up/
NWAYEN reset. See “Strapping Options” section for details.
Activity Pin State LED Definition
Activity – “Toggle”
30 PD# Ipu Power Down. 1 = Normal operation, 0 = Power-down. Active low.
Notes:
1. P = Power supply.
GND = Ground.
I = Input.
I/O = Bidirectional.
Ipd = Input w/ internal pull-down.
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.
Ipu = Input w/ internal pull-up.
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.
O = Output.
KS8721CL Micrel, Inc.
M9999-041405 8 April 2005
Pin Number Pin Name Type
(1)
Pin Function
31 VDDRX P Analog 2.5V power supply. See “Circuit Design Ref. for Power Supply” section for
details.
32 RX- I Receive Input. Differential receive input pins for 100FX, 100BASE-TX, or 10BASE-T.
33 RX+ I Receive Input: Differential receive input pin for 100FX, 100BASE-TX, or 10BASE-T.
34 FXSD/FXEN Ipd/O Fiber Mode Enable / Signal Detect in Fiber Mode. If FXEN = 0, FX mode is
disable. The default is “0”. See “100BT FX Mode” section for more details.
35 GND GND Ground.
36 GND GND Ground.
37 REXT I External resistor (6.49kW ) connects to REXT and GND.
38 VDDRCV P Analog 2.5V power supply. 2.5V power output of voltage regulator. See “Circuit
Design Ref. for Power Supply” section for details.
39 GND GND Ground.
40 TX- O Transmit Outputs: Differential transmit output for 100FX, 100BASE-TX, or
10BASE-T.
41 TX+ O
Transmit Outputs: Differential transmit output for 100FX, 100BASE-TX, or 10BASE-T.
42 VDDTX P Transmitter 2.5V power supply. See “Circuit Design Ref. for Power Supply” section
for details.
43 GND GND Ground.
44 GND GND Ground.
45 XO O XTAL feedback: Used with XI for Xtal application.
46 XI I Crystal Oscillator Input: Input for a crystal or an external 25MHz clock.
If an oscillator is used, XI connects to a 3.3V tolerant oscillator, and X2 is a no-
connect.
47 VDDPLL P Analog PLL 2.5V power supply. See “Circuit Design Ref. for Power Supply”
section for details.
48 RST# Ipu Chip Reset. Active low, minimum of 50µs pulse is required.
Notes:
1. P = Power supply.
GND = Ground.
I = Input.
I/O = Bidirectional.
Ipd = Input w/ internal pull-down.
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.
Ipu = Input w/ internal pull-up.
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.
O = Output.
April 2005 9 M9999-041405
KS8721CL Micrel, Inc.
Strapping Options
(1)
Pin Number Pin Name Type
(2)
Description
6,5, PHYAD[4:1]/ Ipd/O PHY Address latched at power-up/reset. The default PHY address is 00001.
4,3 RXD[0:3]
25 PHYAD0/ Ipu/O
INT#
9
(3)
PCS_LPBK/ Ipd/O Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
RXDV
11
(3)
ISO/RXER Ipd/O Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
21
(3)
RMII/COL Ipd/O Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
22
(3)
RMII_BTB Ipd/O Enable RMII back-to-back mode at power-up/reset. PD (default) = Disable,
CRS PU = Enable.
27 SPD100/ Ipu/O Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)
No FEF/ = 100Mbps. If SPD100 is asserted during power-up/reset, this pin is also latched as
LED1 the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
means no Far_End _Fault.)
28 DUPLEX/ Ipu/O Latched into Register 0h bit 8 during power-up/reset. PD = Half-duplex, PU
LED2 (default) = Full-duplex. If Duplex is pulled up during reset, this pin is also latched as
the Duplex support in register 4h.
29 NWAYEN/ Ipu/O Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/
LED3 reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
30 PD# Ipu Power-Down Enable. PU (default) = Normal operation, PD = Power-Down mode.
Notes:
1. Strap-in is latched during power-up or reset.
2. Ipu = Input w/ internal pull-up.
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.
See “Reference Circuit” section for pull-up/pull-down and float information.
3. Some devices may drive MII pins that are designated as output (PHY) on power up, resulting in incorrect strapping values latched in at reset. It is
recommended that an external pull-down via 1kΩ resistor be used in their applications to augment the 8721's internal pull-down.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

KSZ8721CL-TR

Mfr. #:
Buy KSZ8721CL-TR
Manufacturer:
Microchip Technology / Micrel
Description:
Ethernet ICs 10/100 BASE-TX/FX Physical Layer Transceiver
Lifecycle:
New from this manufacturer.
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