SL2S5302_SL2S5402 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.2 — 27 August 2012
192132 6 of 35
NXP Semiconductors
SL2S5302; SL2S5402
ICODE SLIX-S
7. Mechanical specification
7.1 Wafer specification
See Ref. 6 “General specification for 8” wafer on UV-tape with electronic fail die marking”.
Table 3. Wafer specification
Wafer
Designation each wafer is enscribed with batch number and wafer number
Diameter 200 mm (8 inches)
Thickness 120 m 15 m
Process CMOS 0.14 m
Batch size
25 wafers
Dies per wafer
SL2S5302FUD 110050
SL2S5402FUD 88225
Wafer backside
Material Si
Treatment ground and stress release
Roughness R
a
minimum = 0.5 m
R
t
maximum = 5 m
Chip dimensions
Die size without scribe
SL2S5302FUD 520 m 484 m = 251680 mm
2
SL2S5402FUD 520 m 607 m = 315640 mm
2
Scribe line width
X-dimension 15 m (scribe line width measured between nitride edges)
Y-dimension 15 m (scribe line width measured between nitride edges)
Number of pads 4
Pad location non-diagonal/placed in chip corners
Distance pad to pad LA to LB 400 m
Distance pad to pad LB to TEST
SL2S5302FUD 360 m
SL2S5402FUD 517 m
Passivation on front
Type sandwich structure
Material PE-nitride (on top)
Thickness 1.75 m total thickness of passivation
Au bump
Material >99.9 % pure Au
Hardness 35 HV to 80 HV 0.005
Shear strength >70 MPa
Height 18 m
