TDA8034HN All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3.4 — 29 June 2016 10 of 32
NXP Semiconductors
TDA8034HN
Low power smart card interface
8.7 Activation sequence
The following device activation sequence is applied when using an external clock; see
Figure 7
:
1. Pin CMDVCCN is pulled LOW (t0).
2. The internal oscillator is triggered (t0).
3. The internal oscillator changes to high frequency (t1).
4. V
CC
rises from either 0 V to 3 V or 0 V to 5 V on a controlled slope (t2).
5. Pins I/OUC, AUX1UC and AUX2UC are driven HIGH (t3).
6. The clock on pin CLK is applied to the C3 contact (t4).
7. Pin RST is enabled (t5).
Calculation of the time delays is as follows:
t1 = t0 + 384
1
fosc(int)low
t2 = t1
t3 = t1 + 17T / 2
t4 = driven by host controller; > t3 and < t5
t5 = t1 + 23T / 2
Remark: The value of period T is 64 times the period interval of the internal oscillator at
high frequency (
1
fosc(int)high
); t3 is called t
d(start)
and t5 is called t
d(end)
.
Fig 6. Shutdown and Deep shutdown mode activation/deactivation
001aal139
shutdown
CMDVCCN
VCC_SEL1
VCC_SEL2
mode
(internal pin)
OFFN
PRESN
V
CC
shutdown
deactivation
sequence
shutdown
debounce
deep shutdownactivation activation
TDA8034HN All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3.4 — 29 June 2016 11 of 32
NXP Semiconductors
TDA8034HN
Low power smart card interface
8.8 Deactivation sequence
When a session ends, the microcontroller sets pin CMDVCCN HIGH. The TDA8034HN
then executes an automatic deactivation sequence by counting the sequencer back to the
inactive state (see Figure 8
) as follows:
1. Pin RST is pulled LOW (t11).
2. The clock is stopped, pin CLK is LOW (t12).
3. Pins I/OUC, AUX1UC and AUX2UC are pulled LOW (t13).
4. V
CC
falls to 0 V (t14). The deactivation sequence is completed when V
CC
reaches its
inactive state.
5. V
CC
< 0.4 V (t
deac
)
6. All card contacts become low-impedance to GND. However, pins I/OUC, AUX1UC
and AUX2UC remain pulled up to V
DD
using the 11 k resistor.
7. The internal oscillator returns to its low frequency mode.
Calculation of the time delays is as follows:
t11 = t10 + 3T / 64
t12 = t11 + T / 2
t13 = t11 + T
t14 = t11 + 3T / 2
t
deac
= t11 + 3T / 2 + V
CC
fall time
OSCINT = internal oscillator.
Fig 7. Activation sequence at t3
TDA8034HN All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3.4 — 29 June 2016 12 of 32
NXP Semiconductors
TDA8034HN
Low power smart card interface
Remark: The value of period T is 64 times the period interval of the internal oscillator (i.e.
25 s).
8.9 V
CC
regulator
The V
CC
buffer is able to continuously deliver up to 65 mA at V
CC
= 5V, 3V, or 1.8V.
The V
CC
buffer has an internal overload protection with a threshold value of approximately
120 mA. This detection is internally filtered, enabling spurious current pulses up to
200 mA with a duration of a few milliseconds to be drawn by the card without causing
deactivation. However, the average current value must stay below maximum; see Table 8
.
8.10 Fault detection
The following conditions are monitored by the fault detection circuit:
Short-circuit or high current on pin V
CC
Card removal during transaction
V
DDP
falling
V
DD
falling
V
DD(INTF)
falling
Overheating
Fault detection monitors two different situations:
Outside card sessions, pin CMDVCCN is HIGH: pin OFFN is LOW if the card is not in
the reader and HIGH if the card is in the reader. Any voltage drop on V
DD
is detected
by the voltage supervisor. This generates an internal power-on reset pulse but does
not act upon the pin OFFN signal. The card is not powered-up and short-circuits or
overheating are not detected.
OSCINT = internal oscillator.
Fig 8. Deactivation sequence
001aak995
RST
CLK
I/O
V
CC
XTAL1
OSCINT
CMDVCC
high frequency
t10 t11 t12 t13
t
deact
t14
low frequency

TDA8034HN/C2QL

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Interface - Specialized TDA8034HN/HVQFN24//C2/TRAY SINGLE NDP BAKEABLE
Lifecycle:
New from this manufacturer.
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