TDA8034HN All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3.4 — 29 June 2016 4 of 32
NXP Semiconductors
TDA8034HN
Low power smart card interface
6. Block diagram
ALARMN, CLKUP, EN1, PVCC, EN4, EN3, EN2 and CLK are internal signals.
(1) Optional external resistor bridge, if not required connect pin PORADJ to V
DD(INTF)
Fig 1. Block diagram
001aal136
100 nF
100 nF
100 nF
470 nF
220 nF
10 μF
INTERNAL
OSCILLATOR
THERMAL
PROTECTION
CRYSTAL
OSCILLATOR
RESET
GENERATOR
V
CC
LDO
CLOCK
GENERATOR
I/O
TRANSCEIVER
I/O
TRANSCEIVER
I/O
TRANSCEIVER
CLOCK
CIRCUIT
LEVEL
SHIFTER
C5
CARD
CONNECTOR
C1
C6 C2
C7 C3
C8 C4
SEQUENCER
SUPPLY
INTERNAL
REFERENCE
VOLTAGE
SENSE
12
GND
EN1
ALARMN
PRESN
8
PORADJ 18
RSTIN
3
CMDVCCN
5
OFFN
19
CLKDIV1
6
CLKDIV2
7
VCC_SEL2
2
VCC_SEL1
4
I/OUC
20
21
22
CLKUP
EN4
12423
XTAL2
AUX2UC
AUX1UC
XTAL1
V
DD(INTF)
EN3
EN2
CLK
PVCC
I/O
9
CLK
13
RST
14
V
CC
15
AUX1
10
AUX2
11
17
V
DD
16
V
DDP
R2
R1
V
DD(INTF)
(1)
TDA8034HN
TDA8034HN All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3.4 — 29 June 2016 5 of 32
NXP Semiconductors
TDA8034HN
Low power smart card interface
7. Pinning information
7.1 Pinning
7.2 Pin description
Fig 2. Pin configuration
001aal137
TDA8034HN
Transparent top view
CLK
CMDVCCN
CLKDIV1
RST
VCC_SEL1 V
CC
RSTIN V
DDP
VCC_SEL2 V
DD
V
DD(INTF)
PORADJ
CLKDIV2
PRESN
I/O
AUX1
AUX2
GND
XTAL2
XTAL1
AUX2UC
AUX1UC
I/OUC
OFFN
terminal 1
index area
6
13
5
14
4 15
3 16
2 17
1
18
7
8
9
10
11
12
24
23
22
21
20
19
Table 3. Pin description
Symbol Pin Supply Type
[1]
Description
V
DD(INTF)
1V
DD(INTF)
P interface supply voltage
VCC_SEL2 2 V
DD(INTF)
I5V or 3V V
CC
voltage selection control signal:
active LOW: V
CC
= 3 V when pin VCC_SEL1 is HIGH
active HIGH: V
CC
= 5 V
RSTIN 3 V
DD(INTF)
I microcontroller card reset input; active HIGH
VCC_SEL1 4 V
DD(INTF)
I 1.8 V V
CC
voltage selection control signal:
active LOW: V
CC
= 1.8 V
active HIGH: disables 1.8 V selection
CMDVCCN 5 V
DD(INTF)
I microcontroller start activation sequence input; active LOW
CLKDIV1 6 V
DD(INTF)
I sets the clock frequency on pin CLK in association with pin CLKDIV2; see Table 4
CLKDIV2 7 V
DD(INTF)
I sets the clock frequency on pin CLK in association with pin CLKDIV1; see Table 4
PRESN 8 V
DD(INTF)
I card presence contact input; active LOW
[2]
I/O 9 V
CC
I/O card input/output data line (C7)
[3]
AUX1 10 V
CC
I/O auxiliary card input/output data line (C4)
[3]
AUX2 11 V
CC
I/O auxiliary card input/output data line (C8)
[3]
GND 12 - G ground
CLK 13 V
CC
O card clock (C3)
RST 14 V
CC
O card reset (C2)
V
CC
15 V
CC
P card supply (C1); decouple to pin GND using one 470 nF capacitor close to pin V
CC
and one 220 nF capacitor close to card socket contact C1 with an ESR < 100 m
TDA8034HN All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3.4 — 29 June 2016 6 of 32
NXP Semiconductors
TDA8034HN
Low power smart card interface
[1] I = input, O = output, I/O = input/output, G = ground and P = power supply.
[2] If pin PRESN is LOW, the card is considered to be present. During card insertion, debouncing can occur on these signals. To counter
this, the TDA8034HN has a built-in debouncing timer (typically 8 ms).
[3] Uses an internal 11 k pull-up resistor connected to pin V
CC
.
[4] Uses an internal 20 k pull-up resistor connected to pin V
DD(INTF)
.
[5] Uses an internal 10kW pull-up resistor connected to pin V
DD(INTF)
8. Functional description
Remark: Throughout this document the ISO 7816 terminology conventions have been
adhered to and it is assumed that the reader is familiar with these.
8.1 Power supplies
The power supply voltage ranges are as follows:
V
DDP
: 4.85 V to 5.5 V when VCC_SEL2 is HIGH (V
CC
= 5 V)
V
DDP
: 3 V to 5.5 V when VCC_SEL2 is LOW (V
CC
= 3 V) or when VCC_SEL1 is LOW
(V
CC
= 1.8 V)
V
DD
: 2.7 V to 3.6 V
All interface signals to the system controller are referenced to V
DD(INTF)
. All card contacts
remain inactive during power up or power down. After powering up the device, pin OFFN
remains LOW until pin CMDVCCN is set HIGH and pin PRESN is LOW. During power
down, pin OFFN goes LOW when V
DDP
falls below the falling threshold voltage (V
th
).
The internal oscillator frequency (f
osc(int)
) is only used during the activation sequences.
When the card is not activated (pin CMDVCCN is HIGH), the internal oscillator is in low
frequency mode to reduce power consumption.
This device has a Low Drop-Off (LDO) voltage regulator connected to pin V
CC
, and is
used instead of a DC-to-DC converter. It ensures a minimum V
CC
of 4.75 V and that the
power supply voltage on pin V
DDP
does not fall below 4.85 V when pin VCC_SEL2 is
HIGH, for a maximum load current of 65 mA.
V
DDP
16 V
DDP
P low-dropout regulator input supply voltage
V
DD
17 V
DD
P digital supply voltage
PORADJ 18 V
DD(INTF)
I power-on reset threshold adjustment input using an optional external resistor bridge
OFFN 19 V
DD(INTF)
O NMOS interrupt to microcontroller
[4]
; active LOW; see Section 8.10 on page 12
I/OUC 20 V
DD(INTF)
I/O microcontroller input/output data line
[5]
AUX1UC 21 V
DD(INTF)
I/O auxiliary microcontroller input/output data line
[5]
AUX2UC 22 V
DD(INTF)
I/O auxiliary microcontroller input/output data line
[5]
XTAL1 23 V
DD
I crystal connection input
XTAL2 24 V
DD
O crystal connection output
Table 3. Pin description
…continued
Symbol Pin Supply Type
[1]
Description

TDA8034HN/C2QL

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Interface - Specialized TDA8034HN/HVQFN24//C2/TRAY SINGLE NDP BAKEABLE
Lifecycle:
New from this manufacturer.
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