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S1R72U16B08E200

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
6. Pin Functions
10 EPSON S1R72U16 Data Sheet (Rev. 2.00)
DEBUG I/F (HVDD system)
BGA QFP Name I/O RESET Details
H1 17 DBGDCLK O High Not used (*1)
H2 18 DBGDT BI(PU) - Not used (*2)
H3 19 DBGST O Low Not used (*1)
PU: Using pull-up I/O
*1: Set to open or pull-up.
*2: The LSI features internal pull-up, but an external pull-up of approximately 10 kΩ is recommended.
GPIO (IOVDD system)
BGA QFP Name I/O RESET Details
E4 26
PORT00
(ATAxATAPI)
I -
Setting pin
1: ATA mode, 0: ATAPI mode
E5 27
PORT01
(2x1)
I -
Setting pin
1: two-device mode, 0: one-device mode
F4 25
PORT02
(CPUxIDE)
I -
Setting pin
1: CPU mode, 0: IDE mode
G6 35
PORT10
(XChgInt)
O -
Storage device connection detection interrupt
1: -, 0: Connection detection
F6 36
PORT11
(XCD0)
O -
Storage device 0 detection
1: -, 0: Detect
H7 37
PORT12
(XCD1)
O -
Storage device 1 detection
1: -, 0: Detect
G7 38
PORT13
(PLL_Locked)
O -
PLL oscillation start
1: Oscillation start, 0: No oscillation
H8 39
PORT14
(ComplianceErr0)
O -
Unsupported Device
1: Error, 0: -
G8 42
PORT15
(ComplianceErr1)
O -
Too Many Devices
1: Error, 0: -
G9 43
PORT16
(ComplianceErr2)
O -
Too Many Hubs
1: Error, 0: -
F8 44
PORT17
(ComplianceErr3)
O -
VBUS Over Current
1: Error, 0: -
POWER
BGA QFP Name Voltage Details
D1, F2, J2 5, 9, 21 HVDD 3.3V USB, UART, DEBUG I/F power supply
A6, H9 41, 66 IOVDD 3.3V to 1.8V IDE I/F and GPIO power supply
B1, G1, B3,
J8, B9
1, 10, 40,
60, 76
LVDD 1.8V
Internal power supply, TEST power supply, OSC
power supply
B2, C2, E2,
G2, D3, E3,
J7, D9
2, 4, 7, 11,
14, 34, 53,
73
VSS 0V GND
6. Pin Functions
S1R72U16 Data Sheet (Rev. 2.00) EPSON 11
6.2 CPU Mode
CPU memory bus I/F (IOVDD system)
BGA QFP Name I/O RESET Details
D8 54 CA2 IN -
D6 52 CA1 IN -
D5 51 CA0 IN -
Address
E6 50 XCS IN - Chip selection
E7 49 CA3 IN - Address
J6 33 XRD IN - Read strobe
G5 31 XWR IN - Write strobe
H5 30 XDREQ OUT High DMA transfer request
J5 29 XDACK IN - DMA transfer acknowledge
H6 32 - OUT(PU) Hi-z Not used (*)
F5 28 XINT OUT High Interrupt request
E9 48 XHRESET IN - Bus reset
E8 47 - BI(PU) Hi-z Not used (*)
F7 46 - BI(PU) Hi-z Not used (*)
F9 45 CSEL IN - Drive selection
D7 55 CD15 BI Hi-Z
C9 56 CD14 BI Hi-Z
C8 57 CD13 BI Hi-Z
C7 58 CD12 BI Hi-Z
B8 59 CD11 BI Hi-Z
A8 61 CD10 BI Hi-Z
B7 62 CD9 BI Hi-Z
A7 63 CD8 BI Hi-Z
C6 64 CD7 BI Hi-Z
B6 65 CD6 BI Hi-Z
C5 67 CD5 BI Hi-Z
B5 68 CD4 BI Hi-Z
A5 69 CD3 BI Hi-Z
D4 70 CD2 BI Hi-Z
C4 71 CD1 BI Hi-Z
B4 72 CD0 BI Hi-Z
Data bus
PU: Using pull-up I/O
* Set to open or pull-up. LSI internal pull-up resistor is enabled in CPU mode.
For detailed information on pins other than those described above, see “6.1 IDE Mode”.
7. Register
12 EPSON S1R72U16 Data Sheet (Rev. 2.00)
7. Register
7.1 Register Map
7.1.1 IDE Mode Register Map
XHCS1_T XHCS0_T HDA2_T HDA1_T HDA0_T Read Write
Pin Register
L H L L L none
L H L L H none
L H L H L none
L H L H H none
L H H L L none
L H H L H none
L H H H L Alternate Status
L H H H H none
LH L L L Data (16bit)
LH L L H Error
LH L H L Sector Count
LH L H H LBA Low
LH H L L LBA Mid
LH H L H LBA High
LH H H L Device
LH H H H Command
Device Control
Status
Feature
Figure 7.1 IDE mode register map
7.1.2 CPU Mode Register Map
XCS CA3 CA2 CA1 CA0 Read Write
Pin Register
L H L L L none
L H L L H none
L H L H L none
L H L H H none
L H H L L none
L H H L H none
L H H H L Alternate Status
L H H H H none
L L L L Data (16bit)
L L L H Error
L L H L Sector Count
L L H H LBA Low
L H L L LBA Mid
L H L H LBA High
L H H L Device
L H H H Command
Device Control
Status
Feature
L
L
L
L
L
L
L
L
Figure 7.2 CPU mode register map
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

S1R72U16B08E200

Mfr. #:
Buy S1R72U16B08E200
Manufacturer:
Epson ICs
Description:
USB Interface IC USB HS Host cntrlr embedded USB driver
Lifecycle:
New from this manufacturer.
Delivery:
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