8. Electrical Characteristics
24 EPSON S1R72U16 Data Sheet (Rev. 2.00)
8.4.6 CPUIF Timing (DMA)
XCS, CA[3:0]
tasu
Code Details Min Typ Max Units
tcy Cycle 120/130 - - ns
XRD, XWR
CD[15:0](write)
XDREQ
XDACK
CD[15:0](read)
tspw
twds
twd
h
trds trdh
trbf
tahd
tcy
tasu Address setup 25/25 - - ns
tspw XRD/XWR pulse width 70/75 - - ns
trds Read data setup 20/15 - - ns
trdh Read data hold 5/5 - - ns
trbf Bus release 30/30-- ns
twds Write data setup 20/25 - - ns
twdh Write data set hold 10/10 - - ns
tahd Address hold 10/10 - - ns
DMA read/write
tnpw
trdl
tach
tacs
tspw XRD/XWR negate pulse width 25/30 - - ns
trdl XDREQ delay 35/45-- ns
tacs XDACK setup 0/0 - - ns
tach XDACK hold 5/5 - - ns
* When using IOVDD = 3.0 V to 3.6 V / When using IOVDD = 1.8 V to 3.0 V (wide range)
Code Details Min Typ Max Units
trdh Read data hold time 5/5 *1 - - ns
tahd Address hold time 0/0 - - ns
* When using IOVDD = 3.0 V to 3.6 V / When using IOVDD = 1.8 V to 3.0 V (wide range)
*1: The read data hold time will be 0 ns for address chan
es if the address hold time is less than 5 ns.
S1R72U16***E200 AC characteristics
Note: The definition of AC shown above uses the description format specified in ATA standards. Consider the valid data
output start time in a read operation as follows:
70 (XRD pulse width: min) -20 (read data setup: min) = 50 ns (when IOVDD = 3.0 to 3.6 V)
