7. Register
14 EPSON S1R72U16 Data Sheet (Rev. 2.00)
7.2.6 LBA Mid Register
This register permits reads/writes and sets LBA [15:8].
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
LBA Mid Byte
7.2.7 LBA High Register
This register permits reads/writes and sets LBA [23:16].
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
LBA High Byte
7.2.8 Device Register
This register permits reads/writes. Bit assignments and values vary, depending on the
ATA/ATAPI command.
Obsolute # Obsolute DEV # # # #
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
7.2.9 Status Register
This read-only register is updated to indicate status when a command is executed. Reading this
register when the HINTRQ_T signal is asserted cause to nagate the HINTRQ_T signal.
BSY DRDY DF # DRQ Obsolute ChgInt ERR
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Bit 1 ChgInt
This bit, unique to this LSI, indicates whether a USB storage device is connected (using the
bit dropped as of AT Attachment with Packet Interface – 6 (ATA/ATAPI-6)). The XChgInt
signal status can be read off inverted. For detailed information, see the S1R72U16
Technical Manual.
7.2.10 Command Register
This
is a write-only register. The register command is executed immediately on being
written. Issuing the command (writing to this register) when the HINTRQ_T signal is
asserted cause to nagate the HINTRQ_T signal.
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Command Code
