ZL30117 Data Sheet
10
Zarlink Semiconductor Inc.
1.0 Functional Description
The ZL30117 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and
synchronization for network interface cards. The DPLL is capable of locking to one of three input references and
provides a wide variety of synchronized output clocks and frame pulses.
1.1 DPLL Features
The Digital Phase-Locked Loop synchronizes to one of the qualified references and provides automatic or
manual hitless reference switching and a holdover function when no qualified references are available. It
provides a highly configurable set of features which are configurable through the serial interface. A summary of
these features are shown in Table 1.
Feature DPLL
Modes of Operation Free-run, Normal (locked), Holdover
Loop Bandwidth User selectable: 14 Hz, 28 Hz, or wideband
1
(890 Hz / 56 Hz / 14 Hz)
1. In the wideband mode, the loop bandwidth depends on the frequency of the reference input. For reference frequencies equal to or
greater than 64 kHz, the loop bandwidth = 890 Hz. For reference frequencies equal to or greater than 8 kHz and less than 64 kHz, the
loop bandwidth = 56 Hz. For reference frequencies equal to 2 kHz, the loop bandwidth is equal to 14 Hz.
Phase Slope Limiting User selectable: 885 ns/s, 7.5 μs/s, 61 μs/s, or unlimited
Pull-in Range Fixed: 130 ppm
Reference Inputs Ref0, Ref1, Ref2
Sync Inputs Sync0, Sync1, Sync2
Input Reference Frequencies 2 kHz, N * 8 kHz up to 77.76 MHz
Supported Sync Input
Frequencies
166.67 Hz, 400 Hz, 1 kHz, 2 kHz, 8 kHz, 64 kHz.
Input Reference
Selection/Switching
Automatic (based on programmable priority and revertiveness), or manual
selection
Hitless Reference Switching Can be enabled or disabled
Output Clocks diff_p/n, sdh_clk, p_clk
Output Frame Pulses sdh_fp, p_fp synchronized to active sync reference.
Supported Output Clock
Frequencies
As listed in Table 4
Supported Output Frame
Pulse Frequencies
As listed in Table 4
External Pins Status
Indicators
Lock, Holdover
Table 1 - DPLL Features
ZL30117 Data Sheet
11
Zarlink Semiconductor Inc.
1.2 DPLL Mode Of Operation
The DPLL supports three modes of operation - free-run, normal, and holdover. The mode of operation can be
manually set or controlled by an automatic state machine as shown in Figure 2.
Figure 2 - Automatic Mode State Machine
Free-run
The free-run mode occurs immediately after a reset cycle or when the DPLL has never been synchronized to a
reference input. In this mode, the frequency accuracy of the output clocks is equal to the frequency accuracy of the
external master oscillator.
Lock Acquisition
The input references are continuously monitored for frequency accuracy and phase regularity. If at least one of the
input references is qualified by the reference monitors, then the DPLL will begin lock acquisition on that input. Given
a stable reference input, the ZL30117 will enter in the Normal (locked) mode.
Normal (locked)
The usual mode of operation for the DPLL is the normal mode where the DPLL phase locks to a selected qualified
reference input and generates output clocks and frame pulses with a frequency accuracy equal to the frequency
accuracy of the reference input. While in the normal mode, the DPLLs clock and frame pulse outputs comply with
the MTIE and TDEV wander generation specifications as described in Telcordia and ITU-T telecommunication
standards.
Holdover
When the DPLL operating in the normal mode loses its reference input, and no other qualified references are
available, it will enter the holdover mode and continue to generate output clocks based on historical frequency data
collected while the DPLL was synchronized. The transition between normal and holdover modes is controlled by
the DPLL so that its initial frequency offset is better than 100 ppb. The frequency drift after this transition period is
dependant on the frequency drift of the external master oscillator.
Reset
Another reference is
qualified and available
for selection
Phase lock on
the selected
reference is
achieved
Lock
Acquisition
Normal
(Locked)
No references are
qualified and
available for
selection
Free-Run
Holdover
Selected reference
fails
All references are monitored
for frequency accuracy and
phase regularity, and at least
one reference is qualified.
Normal
(Locked)
ZL30117 Data Sheet
12
Zarlink Semiconductor Inc.
1.3 Ref and Sync Inputs
There are three reference clock inputs (ref0 to ref2) available to the DPLL. Reference selection can be controlled
using a built-in state machine or set in a manual mode.The selected reference input is used to synchronize the
output clocks.
Figure 3 - Reference and Sync Inputs
In addition to the reference inputs, the DPLL has three optional frame pulse synchronization inputs (sync0 to
sync2) used to align the output frame pulses. The sync
n
input is selected with its corresponding ref
n
input, where n
= 0, 1, or 2. Note that the sync input cannot be used to synchronize the DPLL, it only determines the alignment of
the frame pulse outputs. An example of output frame pulse alignment is shown in Figure 4.
Figure 4 - Output Frame Pulse Alignment
ref2:0
sync2:0
DPLL
ref
n
diff_clk/sdh_clk/p_clk
sdh/p_fp
Without a frame pulse
signal at the sync input,
the output frame pulses
will align to any arbitrary
cycle of its associated
output clock.
sync
n
- no frame pulse signal present
When a frame pulse
signal is present at the
sync input, the DPLL
will align the output
frame pulses to the
output clock edge that is
aligned to the input
frame pulse.
ref
n
sync
n
n = 0, 1, 2
n = 0, 1, 2
diff_clk/sdh_clk/p_clk
sdh_fp/p_fp

ZL30117GGG2

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products Pb Free SONET/SDH PLL Line Card Synch.
Lifecycle:
New from this manufacturer.
Delivery:
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