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ZL30117GGG2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
ZL30117 Data Sheet
19
Zarlink Semiconductor Inc.
28 dpll_lock_holdover_status 04 DPLL lock and holdover status register R
29 Reserved 03 Leave as default R/W
2A -
35
Reserved Leave as default
Programmable Synthesizer Configuration Registers
36 p_enable 8F Control register to enable the p_clk and p_fp
outputs of the programmable synthesizer
R/W
37 p_run 0F Control register to generate p_clk, p_fp R/W
38 p_freq_0 00 Control register for the [7:0] bits of the N of
N*8k clk
R/W
39 p_freq_1 01 Control register for the [13:8] bits of the N of
N*8k clk
R/W
3A p_clk_offset90 00 Control register for the p_clk phase position
coarse tuning
R/W
3B Reserved Leave as default
3C Reserved Leave as default
3D p_offset_fine 00 Control register for the output/output phase
alignment fine tuning for the programmable
synthesizer
R/W
3E p_fp_freq 05 Control register to select the p_fp frame pulse
frequency
R/W
3F p_fp_type 83 Control register to select p_fp type R/W
40 p_fp_offset_0 00 Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/262.14 MHz
R/W
41 p_fp_offset_1 00 Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/262.14 MHz
R/W
42 p_fp_offset_2 00 Bits [21:16] of the programmable frame pulse
phase offset in multiples of 8 kHz cycles
R/W
43 -
4F
Reserved Leave as default
SDH Configuration Registers
50 sdh_enable 8F Control register to enable sdh_clk and sdh_fp R/W
51 sdh_run 0F Control register to generate sdh_clk and
sdh_fp
R/W
52 sdh_clk_div 42 Control register for the sdh_clk frequency
selection
R/W
53 sdh_clk_offset90 00 Control register for the sdh_clk phase position
coarse tuning
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
Table 5 - Register Map (continued)
ZL30117 Data Sheet
20
Zarlink Semiconductor Inc.
54 Reserved Leave as default
55 sdh_offset_fine 00 Control register for the output/output phase
alignrment fine tuning for sdh path
R/W
56 sdh_fp_freq 05 Control register to select the sdh_fp frame
pulse frequency
R/W
57 sdh_fp_type 23 Control register to select sdh_fp type R/W
58 sdh_fp_offset_0 00 Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
59 sdh_fp_offset_1 00 Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
5A sdh_fp_offset_2 00 Bits [21:16] of the programmable frame pulse
phase offset in multiples of 8 kHz cycles
R/W
5B -
5F
Reserved Leave as default
Differential Output Configuration
60 diff_clk_ctrl A3 Control register to enable diff_clk R/W
61 diff_clk_sel 53 Control register to select the diff_clk frequency R/W
External Feedback Configuration
62 Reserved Leave as default
63 fb_offset_fine F5 Control register for the output/output phase
alignment fine tuning
R/W
64 reserved
Custom Input Frequencies
65 ref_freq_mode_0 00 Control register to set whether to use auto
detect, CustomA or CustomB for ref0 to ref2
R/W
66 Reserved Leave as default
67 custA_mult_0 00 Control register for the [7:0] bits of the custom
configuration A. This is the N integer for the
N*8kHz reference monitoring.
R/W
68 custA_mult_1 00 Control register for the [13:8] bits of the custom
configuration A. This is the N integer for the
N*8kHz reference monitoring.
R/W
69 custA_scm_low 00 Control register for the custom configuration A:
single cycle SCM low limiter
R/W
6A custA_scm_high 00 Control register for the custom configuration
A: single cycle SCM high limiter
R/W
6B custA_cfm_low_0 00 Control register for the custom configuration
A: The [7:0] bits of the single cycle CFM low
limit
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
Table 5 - Register Map (continued)
ZL30117 Data Sheet
21
Zarlink Semiconductor Inc.
6C custA_cfm_low_1 00 Control register for the custom configuration
A: The [15:0] bits of the single cycle CFM low
limit
R/W
6D custA_cfm_hi_0 00 Control register for the custom configuration
A: The [7:0] bits of the single cycle CFM high
limit
R/W
6E custA_cfm_hi_1 00 Control register for the custom configuration
A: The [15:0] bits of the single cycle CFM high
limiter
R/W
6F custA_cfm_cycle 00 Control register for the custom configuration
A: CFM reference monitoring cycles - 1
R/W
70 custA_div 00 Control register for the custom configuration
A: enable the use of ref_div4 for the CFM and
PFM inputs
R/W
71 custB_mult_0 00 Control register for the [7:0] bits of the custom
configuration B. This is the 8 k integer for the
N*8kHz reference monitoring.
R/W
72 custB_mult_1 00 Control register for the [13:8] bits of the custom
configuration B. This is the 8 k integer for the
N*8kHz reference monitoring.
R/W
73 custB_scm_low 00 Control register for the custom configuration B:
single cycle SCM low limiter
R/W
74 custB_scm_high 00 Control register for the custom configuration
B: single cycle SCM high limiter
R/W
75 custB_cfm_low_0 00 Control register for the custom configuration
B: The [7:0] bits of the single cycle CFM low
limiter.
R/W
76 custB_cfm_low_1 00 Control register for the custom configuration
B: The [15:0] bits of the single cycle CFM low
limiter.
R/W
77 custB_cfm_hi_0 00 Control register for the custom configuration
B: The [7:0] bits of the single cycle CFM high
limiter.
R/W
78 custB_cfm_hi_1 00 Control register for the custom configuration
B: The [15:0] bits of the single cycle CFM high
limiter.
R/W
79 custB_cfm_cycle 00 Control register for the custom configuration
B: CFM reference monitoring cycles - 1
R/W
7A custB_div 00 Control register for the custom configuration
B: enable the use of ref_div4 for the CFM and
PFM inputs
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
Table 5 - Register Map (continued)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

ZL30117GGG2

Mfr. #:
Buy ZL30117GGG2
Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products Pb Free SONET/SDH PLL Line Card Synch.
Lifecycle:
New from this manufacturer.
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