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ZL30117GGG2
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
ZL301
17
Data Sheet
List of Figures
4
Zarlink Semicond
uctor Inc.
Figure 1 - Block Diagram
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1
Figure 2 - Automat
ic Mode S
tate Machine
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1
1
Figure 3 - Reference and Sync Input
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. 12
Figure 4 - Output Frame Pulse Alignment . .
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Figure 5 - Behaviour of the Guard Soak T
i
mer during CFM or
SCM Failures . . . . . . . .
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.
14
Figure 6 - Output Configuration .
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. 15
Figure 7 - Phase Delay Adj
ustments . . . . . .
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ZL301
17
Data Sheet
List of Tables
5
Zarlink Semicond
uctor Inc.
T
able 1 - DPLL Features
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. 10
T
able 2 - Set of Pre-Defined Auto-Detec
t Clock Frequencies
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T
able 3 - Set of Pre-Defined Auto-Detec
t Sync Frequencies
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T
able 4 - Output Clock and Frame Pulse
Frequencies
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T
able 5 - Register Map
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. 17
ZL301
17
Data Sheet
6
Zarlink Semicond
uctor Inc.
Changes Summary
The following table captu
res the changes from the February 2006 issue.
Page
Item
Change
20-21
Software Register Description
Changed
the naming and description of the frame
pulse delay of
fset register
s to clearly show that
they form a 22-bit register
spread out over 3 8-bit
registers. The 22-bit regist
er must be considered a
multi-byte register during a
read or write operation.
This affe
cts registers 0x40-0x42, and 0x58-0
x5A.
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
ZL30117GGG2
Mfr. #:
Buy ZL30117GGG2
Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products Pb Free SONET/SDH PLL Line Card Synch.
Lifecycle:
New from this manufacturer.
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