OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

ZL30117GGG2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
ZL30117 Data Sheet
16
Zarlink Semiconductor Inc.
1.6 Configurable Input-to-Output and Output-to-Output Delays
The ZL30117 allows programmable static delay compensation for controlling input-to-output and output-to-output
delays of its clocks and frame pulses.
Both the SONET/SDH APLL and the Programmable Synthesizer can be configured to lead or lag the selected input
reference clock using the DPLL Fine Delay. The delay is programmed in steps of 119.2 ps with a range of -128 to
+127 steps giving a total delay adjustment in the range of -15.26 ns to +15.14 ns. Negative values delay the output
clock, positive values advance the output clock.
In addition to the delay introduced by the DPLL Fine Delay, the SONET/SDH APLL and programmable synthesizer
have the ability to add their own fine delay adjustments using the P Fine Delay and SDH Fine Delay. These delays
are also programmable in steps of 119.2 ps with a range of -128 to +127 steps.
In addition to these delays, the single-ended output clocks of the SONET/SDH and Programmable synthesizers
can be independently offset by 90, 180 and 270 degrees using the Coarse Delay, and the SONET/SDH differential
outputs can be independently delayed by -1.6 ns, 0 ns, +1.6 ns or +3.2 ns using the Diff Delay. The output frame
pulses (sdh_clk, p_fp) can be independently offset with respect to each other using the FP Delay.
Figure 7 - Phase Delay Adjustments
DPLL
P Fine Delay
p_clk
p_fp
Programmable
Synthesizer
Coarse Delay
FP Delay
Diff Delay
diff_clk_p/n
SONET/SDH
APLL
sdh_clk
sdh_fp
SDH Fine Delay
Coarse Delay
FP Delay
DPLL Fine Delay
Feedback
Synthesizer
ZL30117 Data Sheet
17
Zarlink Semiconductor Inc.
2.0 Software Configuration
The ZL30117 is mainly controlled by accessing software registers through the serial peripheral interface (SPI). The
device can be configured to operate in a highly automated manner which minimizes its interaction with the system’s
processor, or it can operate in a manual mode where the system processor controls most of the operation of the
device.
The following table provides a summary of the registers available for status updates and configuration of the device.
.
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
Miscellaneous Registers
00 id_reg A1 Chip and version identification and reset ready
indication register
R
01 use_hw_ctrl 00 Allows some functions of the device to be
controlled by hardware pins
R/W
Interrupts
02 ref_fail_isr FF Reference failure interrupt service register R
03 dpll_isr 70 DPLL interrupt service register StickR
04 Reserved Leave as default
05 ref_mon_fail_0 FF Ref0 and ref1 failure indications StickR
06 ref_mon_fail_1 FF Ref2 failure indication. StickR
07 Reserved Leave as default
08 Reserved Leave as default
09 ref_fail_isr_mask 00 Reference failure interrupt service register
mask
R/W
0A dpll_isr_mask 00 DPLL interrupt service register mask R/W
0B Reserved Leave as default
0C ref_mon_fail_mask_0 FF Control register to mask each failure indicator
for ref0 and ref1
R/W
0D ref_mon_fail_mask_1 FF Control register to mask failure indicator for
ref2
R/W
0E Reserved Leave as default
0F Reserved Leave as default
Reference Monitor Setup
10 detected_ref_0 FF Ref0 and ref1 auto-detected frequency value
status register
R
11 detected_ref_1 FF Ref2 auto-detected frequency value status
register
R
12 Reserved Leave as default R
13 Reserved Leave as default R
Table 5 - Register Map
ZL30117 Data Sheet
18
Zarlink Semiconductor Inc.
14 detected_sync_0 EE Sync0 and sync1 auto-detected frequency
value and sync failure status register
R
15 detected_sync_1 0E Sync2 auto-detected frequency value and sync
valid status register
R
16 oor_ctrl_0 33 Control register for the ref0 and ref1 out of
range limit
R/W
17 oor_ctrl_1 33 Control register for the ref2 out of range limit R/W
18 Reserved Leave as default
19 Reserved Leave as default
1A gst_mask FF Control register to mask the inputs to the guard
soak timer for ref0 - ref2
R/W
1B Reserved Leave as default
1C gst_qualif_time 1A Control register for the guard_soak_timer
qualification time and disqualification time for
the references
R/W
DPLL Control
1D dpll_ctrl_0 See
Register
Description
Control register for the DPLL filter control;
phase slope limit, bandwidth and hitless
switching
R/W
1E dpll_ctrl_1 See
Register
Description
Holdover update time, filter_out_en,
freq_offset_en, revert enable
R/W
1F dpll_modesel See
Register
Description
Control register for the DPLL mode of
operation
R/W
20 dpll_refsel 00 DPLL reference selection or reference selection
status
R/W
21 dpll_ref_fail_mask 3C Control register to mask each failure indicator
(SCM, CFM, PFM and GST) used for automatic
reference switching and automatic holdover
R/W
22 dpll_wait_to_restore 00 Control register to indicate the time to restore a
previous failed reference
R/W
23 dpll_ref_rev_ctrl 00 Control register for the ref0 to ref2 enable
revertive signals
R/W
24 dpll_ref_pri_ctrl_0 10 Control register for the ref0 and ref1 priority
values
R/W
25 dpll_ref_pri_ctrl_1 32 Control register for the ref2 priority values R/W
26 Reserved Leave as default
27 Reserved Leave as default
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
Table 5 - Register Map (continued)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

ZL30117GGG2

Mfr. #:
Buy ZL30117GGG2
Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products Pb Free SONET/SDH PLL Line Card Synch.
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet