ZL30117GGG2 Datasheet ZL30117GGG2, ZL30117GGG | P13-P15

ZL30117 Data Sheet

Zarlink Semiconductor Inc.

Each of the ref inputs accept a single-ended LVCMOS clock with a frequency ranging from 2 kHz to 77.76 MHz.

Built-in frequency detection circuitry automatically determines the frequency of the reference if its frequency is

within the set of pre-defined frequencies as shown in Table 2. Custom frequencies definable in multiples of 8 kHz

are also available.

Each of the sync inputs accept a single-ended LVCMOS frame pulse. Since alignment is determined from the rising

edge of the frame pulse, there is no duty cycle restriction on this input, but there is a minimum pulse width

requirement of 5 ns. Frequency detection for the sync inputs is automatic for the supported frame pulse frequencies

shown in Table 3.

1.4 Ref and Sync Monitoring

All input references (ref0 to ref2) are monitored for frequency accuracy and phase regularity. New references are

qualified before they can be selected as a synchronization source, and qualified references are continuously

monitored to ensure that they are suitable for synchronization. The process of qualifying a reference depends on

four levels of monitoring.

Single Cycle Monitor (SCM)

The SCM block measures the period of each reference clock cycle to detect phase irregularities or a missing clock

edge. In general, if the measured period deviates by more than 50% from the nominal period, then an SCM failure

(scm_fail) is declared.

2 kHz

8 kHz

64 kHz

1.544 MHz

2.048 MHz

6.48 MHz

8.192 MHz

16.384 MHz

19.44 MHz

38.88 MHz

77.76 MHz

Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies

166.67 Hz

(48x 125 μs frames)

400 Hz

1 kHz

2 kHz

8 kHz

64 kHz

Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies

ZL30117 Data Sheet

Zarlink Semiconductor Inc.

Coarse Frequency Monitor (CFM)

The CFM block monitors the reference frequency over a measurement period of 30 μs so that it can quickly detect

large changes in frequency. A CFM failure (cfm_fail) is triggered when the frequency has changed by more than 3%

or approximately 30000 ppm.

Precise Frequency Monitor (PFM)

The PFM block measures the frequency accuracy of the reference over a 10 second interval. To ensure an

accurate frequency measurement, the PFM measurement interval is re-initiated if phase or frequency irregularities

are detected by the SCM or CFM. The PFM provides a level of hysteresis between the acceptance range and the

rejection range to prevent a failure indication from toggling between valid and invalid for references that are on the

edge of the acceptance range.

When determining the frequency accuracy of the reference input, the PFM uses the external oscillator’s output

frequency (f

ocsi

) as its point of reference.

Guard Soak Timer (GST)

The GST block mimics the operation of an analog integrator by accumulating failure events from the CFM and the

SCM blocks and applying a selectable rate of decay when no failures are detected.

As shown in Figure 5, a GST failure (gst_fail) is triggered when the accumulated failures have reached the upper

threshold during the disqualification observation window. When there are no CFM or SCM failures, the accumulator

decrements until it reaches its lower threshold during the qualification window.

Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures

Sync Ratio Monitor

All sync inputs (sync0 to sync2) are continuously monitored to ensure that there is a correct number of reference

clock cycles within the frame pulse period.

ref

CFM or SCM failures

upper threshold

lower threshold

- disqualification time

- qualification time = n * t

gst_fail

ZL30117 Data Sheet

Zarlink Semiconductor Inc.

1.5 Output Clocks and Frame Pulses

The ZL30117 offers a wide variety of outputs including one low-jitter differential LVPECL clock (diff_clk_p/n), one

SONET/SDH LVCMOS (sdh_clk) output clock and one programmable LVCMOS (p_clk) output clock. In addition to

the clock outputs, one LVCMOS SONET/SDH frame pulse output (sdh_fp) and one LVCMOS programmable frame

pulse (p_fp) is also available.

Figure 6 - Output Configuration

The supported frequencies for the output clocks and frame pulses are shown in Table 4.

diff_clk_p/n

(LVPECL)

sdh_clk

(LVCMOS)

p_clk

(LVCMOS)

sdh_fp, p_fp

(LVCMOS)

6.48 MHz 6.48 MHz 2 kHz 166.67 Hz

(48x 125 μs frames)

19.44 MHz 9.72 MHz N * 8 kHz (up to 77.76

MHz)

400 Hz

38.88 MHz 12.96 MHz 1 kHz

51.84 MHz 19.44 MHz 2 kHz

77.76 MHz 25.92 MHz 4 kHz

155.52 MHz 38.88 MHz 8 kHz

311.04 MHz 51.84 MHz 32 kHz

622.08 MHz 77.76 MHz 64 kHz

Table 4 - Output Clock and Frame Pulse Frequencies

DPLL

p_clk

p_fp

Programmable

Synthesizer

sdh_clk

sdh_fp

SONET/SDH

APLL

diff_clk_p/n

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

ZL30117GGG2

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Description:

Clock Generators & Support Products Pb Free SONET/SDH PLL Line Card Synch.

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ZL30117GGG2

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