Data Sheet AD7942
Rev. C | Page 15 of 24
CMRR (dB)
40
50
60
70
80
FREQUENCY (kHz)
101 100 1000 10000
VDD = 5V
04657-025
Figure 25. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog
input, IN+, can be modeled as a parallel combination of the
Capacitor C
PIN
and the network formed by the series connection
of R
IN
and C
IN
. C
PIN
is primarily the pin capacitance. R
IN
is typi-
cally 3 kΩ and is a lumped component made up of some serial
resistors and the on resistance of the switches. C
IN
is typically
30 pF and is mainly the ADC sampling capacitor. During the
conversion phase, when the switches are opened, the input imped-
ance is limited to C
PIN
. R
IN
and C
IN
make a 1-pole, low-pass filter
that reduces undesirable aliasing effects and limits the noise.
When the source impedance of the driving circuit is low, the
AD7942 can be driven directly. Large source impedances sig-
nificantly affect the ac performance, especially total harmonic
distortion (THD). The dc performances are less sensitive to the
input impedance. The maximum source impedance depends on
the amount of THD that can be tolerated. The THD degrades as
a function of the source impedance and the maximum input
frequency, as shown in Figure 26.
–115
–110
–105
–100
–95
–90
–85
–80
–75
70
THD (dB)
FREQUENCY (kHz)
250 50 75 100
04657-026
R
S
= 15
R
S
= 50
R
S
= 100
R
S
= 250
R
S
= 500
R
S
= 1k
Figure 26. THD vs. Analog Input Frequency and Source Resistance
Driver Amplifier Choice
Although the AD7942 is easy to drive, the driver amplifier
needs to meet the following requirements:
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7942. Note that the AD7942
produces much less noise than most other 14-bit ADCs
and therefore can be driven by a noisier op amp while
preserving the same or better system performance. The
noise coming from the driver is filtered by the AD7942
analog input circuit, 1-pole, low-pass filter made by R
IN
and C
IN
or by the external filter, if one is used.
For ac applications, the driver needs to have a THD
performance suitable to that of the AD7942. Figure 14
gives the THD vs. frequency that the driver should exceed.
For multichannel multiplexed applications, the driver
amplifier and the AD7942 analog input circuit must be
able to settle for a full-scale step of the capacitor array at a
14-bit level (0.006%). In the amplifier data sheet, settling at
0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 14-bit level
and should be verified prior to driver selection.
Table 8. Recommended Driver Amplifiers
Amplifier Typical Application
ADA4841 Very low noise, small, and low power
AD8021 Very low noise and high frequency
AD8022 Low noise and high frequency
OP184 Low power, low noise, and low frequency
AD8605, AD8615 5 V single supply, low power
AD8519 Small, low power, and low frequency
AD8031 High frequency and low power
Voltage Reference Input
The AD7942 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source (for example,
a reference buffer using the AD8031 or the AD8605), a 10 μF
(X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance, using a low temperature drift ADR43x reference.
If desired, smaller reference decoupling capacitor values
2.2 μF can be used with a minimal impact on performance,
especially on DNL.
AD7942 Data Sheet
Rev. C | Page 16 of 24
Power Supply
The AD7942 is specified over a wide operating range from
2.3 V to 5.5 V. It has, unlike other low voltage converters, a
noise low enough to design a low supply (2.5 V) 14-bit resolu-
tion system with respectable performance. It uses two power
supply pins: a core supply, VDD, and a digital input/output
interface supply, VIO. VIO allows direct interface with any
logic between 1.8 V and VDD. To reduce the supplies needed,
the VIO and VDD can be tied together. The AD7942 is indepen-
dent of power supply sequencing between VIO and VDD.
Additionally, it is insensitive to power supply variations over
a wide frequency range, as shown in Figure 27.
55
60
65
70
75
80
85
90
PSRR (dB)
FREQUENCY (kHz)
10 1000100 10000
04657-027
VDD = 5V
Figure 27. PSRR vs. Frequency
The AD7942 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 28. This makes the part
ideal for low sampling rates (even rates of a few hertz) and low
battery-powered applications.
VDD = 5V
VDD = 2.5V
VIO
0
1000
10
0.1
0.001
OPER
A
TING CURRENTA)
10 100 1000 10000 100000 1000000
SAMPLING RATE (SPS)
04657-028
Figure 28. Operating Current vs. Sampling Rate
Supplying the ADC from the Reference
For simplified applications, the AD7942, with its low operating
current, can be supplied directly using the reference circuit, as
shown in Figure 29. The reference line can be driven by either
The system power supply directly,
A reference voltage with enough current output capability,
such as the ADR43x, or
A reference buffer, such as the AD8031, that can also filter
the system power supply (see Figure 29).
AD8031
AD7942
VIOREF VDD
10µF
10
10k
5V
5V
5V
(NOTE 1)
1µF
04657-029
NOTE 1: OPTIONAL REFERENCE BUFFER AND FILTER.
1µF
Figure 29. Example of Application Circuit
DIGITAL INTERFACE
Although the AD7942 has a reduced number of pins, it offers
flexibility in its serial interface modes.
When in
CS
mode, the AD7942 is compatible with SPI, QSPI,
digital hosts, and DSPs (for example, Blackfin® ADSP-BF53x or
ADSP-219x). A 3-wire interface using the CNV, SCK, and SDO
signals minimizes wiring connections, which is useful, for
instance, in isolated applications. A 4-wire interface using the
SDI, CNV, SCK, and SDO signals allows CNV, which initiates
conversions, to be independent of the readback timing (SDI).
This is useful in low jitter sampling or simultaneous sampling
applications.
When in chain mode, the AD7942 provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on
a single data line similar to a shift register.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The
CS
mode is selected if
SDI is high and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is always selected.
In either mode, the AD7942 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a busy signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a busy indicator,
the user must time out the maximum conversion time prior
to readback.
The busy indicator feature is enabled as follows:
In the
CS
mode, if CNV or SDI is low when the ADC
conversion ends (see Figure 33 and Figure 37).
In the chain mode, if SCK is high during the CNV rising
edge (see Figure 41).
Data Sheet AD7942
Rev. C | Page 17 of 24
CS
Mode 3-Wire Without Busy Indicator
This mode is most often used when a single AD7942 is
connected to an SPI-compatible digital host. The connection
diagram is shown in Figure 30 and the corresponding timing
diagram is shown in Figure 31.
With SDI tied to VIO, a rising edge on CNV initiates a conver-
sion, selects the
CS
mode, and forces SDO to high impedance.
When a conversion is initiated, it continues to completion irres-
pective of the state of CNV. For instance, it is useful to bring
CNV low to select other SPI devices, such as analog
multiplexers. However, CNV must be returned high before the
minimum conversion time and held high until the maximum
conversion time to avoid generating the busy signal indicator.
When the conversion is complete the AD7942 enters the acqui-
sition phase and powers down. When CNV goes low, the MSB
is output onto SDO. The remaining data bits are then clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After the
14th SCK falling edge or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
CNV
SCK
SDOSDI
DATA IN
CLK
CONVERT
V
IO
DIGITAL HOST
AD7942
04657-030
Figure 30.
CS
Mode 3-Wire Without Busy Indicator
Connection Diagram (SDI High)
SDO
D13 D12 D11 D1 D0
t
DIS
SCK
123 121314
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSIONACQUISITION
t
CONV
t
CYC
ACQUISITION
SDI = 1
t
CNVH
t
ACQ
t
EN
04657-031
Figure 31.
CS
Mode 3-Wire Without Busy Indicator, Serial Interface Timing (SDI High)

AD7942BCPZRL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 14-Bit 250KSPS PSEUDO DIFF IC
Lifecycle:
New from this manufacturer.
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