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AD7942BCPZRL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Data Sheet AD7942
Rev. C | Page 3 of 24
SPECIFICATIONS
VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, V
REF
= VDD, T
A
= –40°C to +85°C, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
RESOLUTION 14 Bits
ANALOG INPUT
Voltage Range IN+ − IN− 0 V
REF
V
Absolute Input Voltage IN+ −0.1 VDD + 0.1 V
IN− −0.1 +0.1 V
Analog Input CMRR f
IN
= 250 kHz 65 dB
Leakage Current T
A
= 25°C, acquisition phase 1 nA
Input Impedance See the Analog Input section
ACCURACY
No Missing Codes 14 Bits
Differential Linearity Error −0.7 ±0.3 +0.7 LSB
1
Integral Linearity Error −1 ±0.4 +1 LSB
Transition Noise V
REF
= VDD = 5 V 0.33 LSB
Gain Error
2
, T
MIN
to T
MAX
±0.7 ±6 LSB
Gain Error Temperature Drift ±1 ppm/°C
Offset Error
2
, T
MIN
to T
MAX
VDD = 4.5 V to 5.5 V ±0.45 ±3 mV
VDD = 2.3 V to 4.5 V ±0.75 ±4.5 mV
Offset Temperature Drift ±2.5 ppm/°C
Power Supply Sensitivity VDD = 5 V ± 5% ±0.1 LSB
THROUGHPUT
Conversion Rate VDD = 4.5 V to 5.5 V 0 250 kSPS
VDD = 2.3 V to 4.5 V 0 200 kSPS
Transient Response Full-scale step 1.8 μs
AC ACCURACY
Signal-to-Noise Ratio (SNR) f
IN
= 20 kHz, V
REF
= 5 V 84.5 85 dB
3
f
IN
= 20 kHz, V
REF
= 2.5 V 84 dB
Spurious-Free Dynamic Range (SFDR) f
IN
= 20 kHz −100 dB
Total Harmonic Distortion (THD) f
IN
= 20 kHz −100 dB
Signal-to-Noise and Distortion Ratio (SINAD) f
IN
= 20 kHz, V
REF
= 5 V 83 85 dB
f
IN
= 20 kHz, V
REF
= 5 V, −60 dB input 25 dB
f
IN
= 20 kHz, V
REF
= 2.5 V 84 dB
REFERENCE
Voltage Range 0.5 VDD + 0.3 V
Load Current 250 kSPS, V
REF
= 5 V 50 μA
SAMPLING DYNAMICS
−3 dB Input Bandwidth 2 MHz
Aperture Delay VDD = 5 V 2.5 ns
DIGITAL INPUTS
Logic Levels
V
IL
–0.3 +0.3 × VIO V
V
IH
0.7 × VIO VIO + 0.3 V
I
IL
−1 +1 μA
I
IH
−1 +1 μA
AD7942 Data Sheet
Rev. C | Page 4 of 24
Parameter Conditions Min Typ Max Unit
DIGITAL OUTPUTS
Data Format Serial 14 bits straight binary
Pipeline Delay
Conversion results available
immediately after
completed conversion
V
OL
I
SINK
= +500 μA 0.4 V
V
OH
I
SOURCE
= −500 μA VIO − 0.3 V
POWER SUPPLIES
VDD Specified performance 2.3 5.5 V
VIO Specified performance 2.3 VDD + 0.3 V
VIO Range 1.8 VDD + 0.3 V
Standby Current
4, 5
VDD and VIO = 5 V, at 25°C 1 50 nA
Power Dissipation VDD = 2.5 V, 100 SPS throughput 1.25 μW
VDD = 2.5 V, 100 kSPS throughput 1.25 2 mW
VDD = 2.5 V, 200 kSPS throughput 2.5 4 mW
VDD = 5 V, 100 kSPS throughput 3.6 5 mW
VDD = 5 V, 250 kSPS throughput 12.5 mW
TEMPERATURE RANGE
6
Specified Performance T
MIN
to T
MAX
−40 +85 °C
1
LSB means least significant bit. With a 5 V input range, 1 LSB = 305.2 μV.
2
See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.
3
All specifications in decibels are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4
With all digital inputs forced to VIO or GND as required.
5
During acquisition phase.
6
Contact Analog Devices, Inc., sales for an extended temperature range.
Data Sheet AD7942
Rev. C | Page 5 of 24
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V
1
, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated, T
A
= −40°C to +85°C.
Table 3.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Available Data t
CONV
0.5 2.2 μs
Acquisition Time t
ACQ
1.8 μs
Time Between Conversions t
CYC
4 μs
CNV Pulse Width (CS Mode)
t
CNVH
10 ns
SCK Period (CS Mode)
t
SCK
15 ns
SCK Period (Chain Mode) t
SCK
VIO ≥ 4.5 V 17 ns
VIO ≥ 3 V 18 ns
VIO ≥ 2.7 V 19 ns
VIO ≥ 2.3 V 20 ns
SCK Low Time t
SCKL
7 ns
SCK High Time t
SCKH
7 ns
SCK Falling Edge to Data Remains Valid t
HSDO
5 ns
SCK Falling Edge to Data-Valid Delay t
DSDO
VIO ≥ 4.5 V 14 ns
VIO ≥ 3 V 15 ns
VIO ≥ 2.7 V 16 ns
VIO ≥ 2.3 V 17 ns
CNV or SDI Low to SDO D13 MSB Valid (CS Mode)
t
EN
VIO ≥ 4.5 V 15 ns
VIO ≥ 2.7 V 18 ns
VIO ≥ 2.3 V 22 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
t
DIS
25 ns
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
t
SSDICNV
15 ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
t
HSDICNV
0 ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SSCKCNV
5 ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
HSCKCNV
5 ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SSDISCK
3 ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t
HSDISCK
4 ns
SDI High to SDO High (Chain Mode with Busy Indicator) t
DSDOSDI
VIO ≥ 4.5 V 15 ns
VIO ≥ 2.3 V 26 ns
1
See Figure 2 and Figure 3 for load conditions.
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AD7942BCPZRL7

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Buy AD7942BCPZRL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 14-Bit 250KSPS PSEUDO DIFF IC
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New from this manufacturer.
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