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AD7942BCPZRL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
AD7942 Data Sheet
Rev. C | Page 6 of 24
VDD = 2.3 V to 4.5 V
1
, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated, T
A
= −40°C to +85°C.
Table 4.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available t
CONV
0.7 3.2 μs
Acquisition Time t
ACQ
1.8 μs
Time Between Conversions t
CYC
5 μs
CNV Pulse Width (CS Mode)
t
CNVH
10 ns
SCK Period (CS Mode)
t
SCK
25 ns
SCK Period (Chain Mode) t
SCK
VIO ≥ 3 V 29 ns
VIO ≥ 2.7 V 35 ns
VIO ≥ 2.3 V 40 ns
SCK Low Time t
SCKL
12 ns
SCK High Time t
SCKH
12 ns
SCK Falling Edge to Data Remains Valid t
HSDO
5 ns
SCK Falling Edge to Data Valid Delay t
DSDO
VIO ≥ 3 V 24 ns
VIO ≥ 2.7 V 30 ns
VIO ≥ 2.3 V 35 ns
CNV or SDI Low to SDO D13 MSB Valid (CS Mode)
t
EN
VIO ≥ 2.7 V 18 ns
VIO ≥ 2.3 V 22 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
t
DIS
25 ns
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
t
SSDICNV
30 ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
t
HSDICNV
0 ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SSCKCNV
5 ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
HSCKCNV
8 ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SSDISCK
5 ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t
HSDISCK
4 ns
SDI High to SDO High (Chain Mode with Busy Indicator) t
DSDOSDI
36 ns
1
See Figure 2 and Figure 3 for load conditions.
Timing Diagrams
500µA I
OL
500µA I
OH
1.4V
TO SDO
C
L
50pF
04657-002
Figure 2. Load Circuit for Digital Interface Timing
30% VIO
70% VIO
2V OR VIO – 0.5V
1
0.8V OR 0.5V
2
0.8V OR 0.5V
2
2V OR VIO – 0.5V
1
t
DELAY
t
DELAY
NOTES
1
2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
04657-003
Figure 3. Voltage Reference Levels for Timing
Data Sheet AD7942
Rev. C | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Analog Inputs
IN+
1
, IN−
1
GND − 0.3 V to VDD + 0.3 V
or ±130 mA
REF GND − 0.3 V to VDD + 0.3 V
Supply Voltages
VDD and VIO to GND −0.3 V to +7 V
VDD to VIO ±7 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θ
JA
Thermal Impedance
10-Lead MSOP 200°C/W
10-Lead LFCSP_WD 48.7°C/W
θ
JC
Thermal Impedance
10-Lead MSOP 44°C/W
10-Lead LFCSP_WD 2.96°C/W
Lead Temperature
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1
See the Analog Input section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD7942 Data Sheet
Rev. C | Page 8 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04657-004
AD7942
REF
1
VDD
2
IN+
3
IN–
4
GND
5
VIO
10
SDI
9
SCK
8
SDO
7
CNV
6
NOTES
1. PADDLE CONNECTED TO GND. THIS CONNECTION IS NOT
REQUIRED TO MEET THE ELECTRICAL PERFORMANCES.
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
1 REF AI
Reference Input Voltage. The V
REF
range is from 0.5 V to VDD. REF is referred to the GND pin. Decouple REF
as closely as possible to a 10 μF capacitor.
2 VDD P Power Supply.
3 IN+ AI
Analog Input. IN+ is referred to IN−. The voltage range, that is, the difference between IN+ and IN−, is 0 V
to V
REF
.
4 IN− AI Analog Input Ground Sense. Connect IN− to the analog ground plane or to a remote sense ground.
5 GND P Power Supply Ground.
6 CNV DI
Convert Input. This input pin has multiple functions. On its leading edge, CNV initiates the conversions
and selects the interface mode of the part: chain mode or CS mode. In CS mode, CNV enables the SDO pin
when low. In chain mode, the data should be read when CNV is high.
7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9 SDI DI
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to
daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on
SDI is output on SDO with a delay of 14 SCK cycles.
CS
mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the busy
indicator feature is enabled.
10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).
1
AI = analog input, DI = digital input, DO = digital output, and P = power.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD7942BCPZRL7

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Buy AD7942BCPZRL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 14-Bit 250KSPS PSEUDO DIFF IC
Lifecycle:
New from this manufacturer.
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