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AD7942BCPZRL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Data Sheet AD7942
Rev. C | Page 21 of 24
Chain Mode Without Busy Indicator
This mode can be used to daisy-chain multiple AD7942s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register. A connection diagram example using
two AD7942s is shown in Figure 38 and the corresponding
timing diagram is given in Figure 39.
When SDI and CNV are low, SDO is driven low. With SCK
low, a rising edge on CNV initiates a conversion, selects the
chain mode, and disables the busy indicator. In this mode, CNV
is held high during the conversion phase and the subsequent
data readback. When the conversion is complete, the MSB is
output onto SDO and the AD7942 enters the acquisition phase
and powers down. The remaining data bits stored in the inter-
nal shift register are then clocked by subsequent SCK falling
edges. For each ADC, SDI feeds the input of the internal shift
register and is clocked by the SCK falling edge. Each ADC in
the chain outputs its data MSB first and 14 × N clocks are
required to readback the N ADCs. The data is valid on both
SCK edges. Although the rising edge can be used to capture
the data, a digital host also using the SCK falling edge allows
a faster reading rate and consequently more AD7942s in the
chain, provided the digital host has an acceptable hold time.
The maximum conversion rate may be reduced due to the total
readback time. For instance, with a 5 ns digital host setup time
and 3 V interface, up to eight AD7942s running at a conversion
rate of 220 kSPS can be daisy-chained on a 3-wire port.
CNV
SCK
SDOSDI
CLK
CONVERT
DATA IN
DIGITAL HOST
AD7942
B
CNV
SCK
SDOSDI
AD7942
A
04657-038
Figure 38. Chain Mode Without Busy Indicator Connection Diagram
SDO
A
= SDI
B
D
A
13 D
A
12 D
A
11
SCK
1 2 3 262728
t
SSDISCK
t
HSDISCK
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
CNV
D
A
1
12 13
t
SCK
t
SCKL
t
SCKH
D
A
0
15 1614
SDI
A
= 0
SDO
B
D
B
13 D
B
12 D
B
11 D
A
1D
B
1D
B
0D
A
13 D
A
12
t
HSDO
t
DSDO
t
SSCKCNV
t
HSCKCNV
D
A
0
04657-039
Figure 39. Chain Mode Without Busy Indicator, Serial Interface Timing
AD7942 Data Sheet
Rev. C | Page 22 of 24
Chain Mode with Busy Indicator
This mode can also be used to daisy-chain multiple AD7942s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applica-
tions or for systems with a limited interfacing capacity. Data
readback is analogous to clocking a shift register. A connection
diagram example using three AD7942s is shown in Figure 40
and the corresponding timing diagram is given in Figure 41.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, SDO in the near end ADC
(ADC C in Figure 40) is driven high. This transition on SDO
can be used as a busy indicator to trigger the data readback
controlled by the digital host. The AD7942 then enters the
acquisition phase and powers down. The data bits stored in the
internal shift register are then clocked out, MSB first, by subsequent
SCK falling edges. For each ADC, SDI feeds the input of the
internal shift register and is clocked by the SCK falling edge.
Each ADC in the chain outputs its data MSB first, and 14 × N + 1
clocks are required to readback the N ADCs. Although the
rising edge can be used to capture the data, a digital host also
using the SCK falling edge allows a faster reading rate and
consequently more AD7942s in the chain, provided the digital
host has an acceptable hold time. For instance, with a 5 ns digital
host setup time and a 3 V interface, up to eight AD7942s
running at a conversion rate of 220 kSPS can be daisy-chained
to a single 3-wire port.
CNV
SCK
SDOSDI
CLK
CONVERT
DATA IN
IRQ
DIGITAL HOST
AD7942
C
CNV
SCK
SDOSDI
AD7942
B
04657-040
CNV
SCK
SDOSDI
AD7942
A
Figure 40. Chain Mode with Busy Indicator Connection Diagram
04657-041
SDO
A
= SDI
B
D
A
13 D
A
12 D
A
11
SCK
123 35 41 42
t
EN
CONVERSION
A
CQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
CNV = SDI
A
D
A
1
413
t
SCK
t
SCKH
t
SCKL
D
A
0
15 3114
SDO
B
= SDI
C
D
B
13 D
B
12 D
B
11 D
A
1D
B
1D
B
0D
A
13 D
A
12
43
t
SSDISCK
t
HSDISCK
t
HSDO
t
DSDO
SDO
C
D
C
13 D
C
12 D
C
11 D
A
1D
A
0D
C
1D
C
0D
A
12
17 27 2816
29
D
B
1D
B
0D
A
13D
B
13 D
B
12
t
DSDOSDI
t
SSCKCNV
t
HSCKCNV
D
A
0
t
DSDOSDI
t
DSDOSDI
t
DSDOSDI
Figure 41. Chain Mode with Busy Indicator, Serial Interface Timing
Data Sheet AD7942
Rev. C | Page 23 of 24
APPLICATION HINTS
LAYOUT
Design the PCB that houses the AD7942 so that the analog and
digital sections are separated and confined to certain areas of
the board. The pinout of the AD7942, with all its analog signals
on the left side and all its digital signals on the right side, eases
this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7942 is used as a shield. Fast switching signals, such as
CNV or clocks, should never run near analog signal paths.
Avoid crossover of digital and analog signals.
At least one ground plane should be used. It can be common or
split between the digital and analog sections. In the case of being
split, the ground plane should be joined underneath the AD7942.
The AD7942 voltage reference input, REF, has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is accomplished by placing the reference
decoupling ceramic capacitor close to, and ideally right up
against, the REF and GND pins. Connect these pins with wide,
low impedance traces.
Finally, decouple the power supply of the AD7942, VDD and
VIO, with ceramic capacitors, typically 100 nF, placed close to
the AD7942. Connect the capacitors using short and large
traces to provide low impedance paths and to reduce the effect
of glitches on the power supply lines. An example of layout
following these rules is shown in Figure 42 and Figure 43.
EVALUATING THE PERFORMANCE OF AD7942
Other recommended layouts for the AD7942 are outlined in
the evaluation board for the AD7942 (EVAL-AD7942SDZ). The
evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the EVAL-SDP-CB1Z.
04657-042
Figure 42. Layout Example (Top Layer)
04657-043
Figure 43. Layout Example (Bottom Layer)
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AD7942BCPZRL7

Mfr. #:
Buy AD7942BCPZRL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 14-Bit 250KSPS PSEUDO DIFF IC
Lifecycle:
New from this manufacturer.
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