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AD7942BCPZRL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
AD7942 Data Sheet
Rev. C | Page 18 of 24
CS
Mode 3-Wire with Busy Indicator
This mode is most often used when a single AD7942 is
connected to an SPI-compatible digital host with an interrupt
input. The connection diagram is shown in Figure 32 and the
corresponding timing diagram is shown in Figure 33.
With SDI tied to VIO, a rising edge on CNV initiates a conver-
sion, selects the
CS
mode, and forces SDO to high impedance.
SDO is maintained in high impedance until the completion of
the conversion irrespective of the state of CNV. Prior to the
minimum conversion time, CNV can be used to select other
SPI devices, such as analog multiplexers. However, CNV must
be returned low before the minimum conversion time and held
low until the maximum conversion time to guarantee the
generation of the busy signal indicator. When the conversion
is complete, SDO goes from high impedance to low impedance.
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data reading controlled by the
digital host. The AD7942 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After
the optional 15th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CNV
SCK
SDOSDI
DATA IN
IRQ
CLK
CONVERT
V
IO
VIO
DIGITAL HOST
AD7942
04657-032
47kΩ
Figure 32.
CS
Mode 3-Wire with Busy Indicator
Connection Diagram (SDI High)
SDO
D13 D12 D1 D0
t
DIS
SCK
123 131415
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSION
ACQUISITION
t
CONV
t
CYC
t
CNVH
t
ACQ
ACQUISITION
S
DI = 1
04657-033
Figure 33.
CS
Mode 3-Wire with Busy Indicator, Serial Interface Timing (SDI High)
Data Sheet AD7942
Rev. C | Page 19 of 24
CS
Mode 4-Wire Without Busy Indicator
This mode is most often used when multiple AD7942s are
connected to an SPI-compatible digital host. A connection
diagram using two AD7942s is shown in Figure 34 and the
corresponding timing diagram is given in Figure 35.
With SDI high, a rising edge on CNV initiates a conversion,
selects the
CS
mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers.
However, SDI must be returned high before the minimum
conversion time elapses and held high until the maximum
conversion time is completed to avoid generating the busy
signal indicator. When the conversion is complete, the AD7942
enters the acquisition phase and powers down. Each ADC result
can be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK driving edges. The data is valid on
both SCK edges. Although the nondriving edge can be used to
capture the data, a digital host also using the SCK falling edge
allows a faster reading rate, provided it has an acceptable hold
time. After the 14th SCK falling edge or when SDI goes high,
whichever is earlier, SDO returns to high impedance and
another AD7942 can be read.
If multiple AD7942s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
CNV
SCK
SDOSDI
DATA IN
CLK
CS1
CONVERT
CS2
DIGITAL HOST
AD7942
CNV
SCK
SDOSDI
AD7942
04657-034
Figure 34.
CS
Mode 4-Wire Without Busy Indicator Connection Diagram
SDO
D13 D12 D11 D1 D0
t
DIS
SCK
123 262728
t
HSDO
t
DSDO
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
SDI (CS1)
CNV
t
SSDICNV
t
HSDICNV
D1
12 13
t
SCK
t
SCKL
t
SCKH
D0 D13 D12
15 1614
SDI (CS2)
04657-035
Figure 35.
CS
Mode 4-Wire Without Busy Indicator, Serial Interface Timing
AD7942 Data Sheet
Rev. C | Page 20 of 24
CS
Mode 4-Wire with Busy Indicator
This mode is most often used when a single AD7942 is
connected to an SPI-compatible digital host with an interrupt
input and to keep CNV (which is used to sample the analog
input) independent of the signal used to select the data reading.
This requirement is particularly important in applications where
low jitter on CNV is desired. The connection diagram is shown
in Figure 36 and the corresponding timing diagram is given in
Figure 37.
With SDI high, a rising edge on CNV initiates a conversion,
selects the
CS
mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and held low until the maximum conversion time
is completed to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low. With a pull-up on the SDO line this
transition can be used as an interrupt signal to initiate the data
readback controlled by the digital host. The AD7942 then enters
the acquisition phase and powers down. The data bits are then
clocked out, MSB first, by subsequent SCK driving edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host also using the SCK
falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the optional 15th SCK falling edge
or SDI going high, whichever is earlier, the SDO returns to high
impedance.
CNV
SCK
SDOSDI
DATA IN
IRQ
CLK
CONVERT
CS1
VIO
DIGITAL HOST
AD7942
04657-036
47Ω
Figure 36.
CS
Mode 4-Wire with Busy Indicator Connection Diagram
SDO
D13 D12 D1 D0
t
DIS
SCK
1 2 3 131415
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
t
EN
CONVERSION
A
CQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
SDI
CNV
t
SSDICNV
t
HSDICNV
04657-037
Figure 37.
CS
Mode 4-Wire with Busy Indicator, Serial Interface Timing
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD7942BCPZRL7

Mfr. #:
Buy AD7942BCPZRL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 14-Bit 250KSPS PSEUDO DIFF IC
Lifecycle:
New from this manufacturer.
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