8308I Data Sheet
©2015 Integrated Device Technology, Inc December 10, 20152
TABLE 1. PIN DESCRIPTIONS
Number Name Type Description
1, 11, 13, 15,
17, 19, 21, 23
Q0, Q1, Q7, Q6,
Q5, Q4,Q3, Q2
Output Clock outputs. LVCMOS / LVTTL interface levels.
2, 10, 14, 18, 22 GND Power Power supply ground.
3 CLK_SEL Input Pullup
Clock select input. Selects LVCMOS clock input when HIGH.
Selects CLK, nCLK inputs when LOW. See Table 3A.
LVCMOS / LVTTL interface levels.
4 LVCMOS_CLK Input Pullup Clock input. LVCMOS / LVTTL interface levels.
5 CLK Input Pullup Non-inverting differential clock input.
6 nCLK Input Pulldown Inverting differential clock input.
7 CLK_EN Input Pullup Clock enable. LVCMOS / LVTTL interface levels.
8 OE Input Pullup
Output enable. LVCMOS / LVTTL interface levels.
See Table 3B.
9V
DD
Power Power supply pin.
12, 16, 20, 24 V
DDO
Power Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
TABLE 3A. CLOCK SELECT FUNCTION TABLE
TABLE 3C. CLOCK INPUT FUNCTION TABLE
Control Input
Clock Input
CLK_SEL
0 CLK, nCLK is selected
1 LVCMOS_CLK is selected
Inputs Outputs
Input to Output Mode Polarity
CLK_SEL LVCMOS_CLK CLK nCLK Q0:Q7
0 — 0 1 LOW Differential to Single Ended Non Inverting
0 — 1 0 HIGH Differential to Single Ended Non Inverting
0 — 0 Biased; NOTE 1 LOW Single Ended to Single Ended Non Inverting
0 — 1 Biased; NOTE 1 HIGH Single Ended to Single Ended Non Inverting
0 — Biased; NOTE 1 0 HIGH Single Ended to Single Ended Inverting
0 — Biased; NOTE 1 1 LOW Single Ended to Single Ended Inverting
1 0 — — LOW Single Ended to Single Ended Non Inverting
1 1 — — HIGH Single Ended to Single Ended Non Inverting
NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
C
PD
Power Dissipation Capacitance
(per output)
12 pF
R
PULLUP
Input Pullup Resistor 51
kΩ
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
R
OUT
Output Impedance 5 7 12
Ω
TABLE 3B. OE SELECT FUNCTION TABLE
Control Input
Output Operation
OE
0 Outputs Q0:Q7 are in Hi-Z (disabled)
1 Outputs Q0:Q7 are active (enabled)
