3
COMMERCIAL TEMPERATURE RANGE
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
FEBRUARY 4, 2009
PIN CONFIGURATION (CONTINUED)
TQFP (PN120-1, order code: PF)
TOP VIEW
4660 drw03
A
35
A
34
A
33
A
32
V
CC
A
31
A
30
GND
A
29
A
28
A
27
A
26
A
25
A
24
A
23
FWFT
A
22
V
CC
A
21
A
20
A
19
A
18
GND
A
17
A
16
A
15
A
14
A
13
V
CC
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B
35
B
34
B
33
B
32
GND
B
31
B
30
B
29
B
28
B
27
B
26
V
CC
B
25
B
24
GND
B
23
B
22
B
21
B
20
B
19
B
18
GND
B
17
B
16
V
CC
B
15
B
14
B
13
B
12
GND
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
91
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
V
CC
GND
CLKA
ENA
W/RA
CSA
FFA/IRA
EFA/ORA
VCC
AFA
AEA
MBF2
MBA
RST1
FS0
GND
FS1
RST2
MBB
MBF1
V
CC
AEB
AFB
EFB/ORB
FFB/IRB
GND
CSB
W/RB
ENB
CLKB
GND
A
11
A
10
A
9
A
8
A
7
A
6
GND
A
5
A
4
A
3
V
CC
A
2
A
1
A
0
GND
B
0
B
1
B
2
B
3
B
4
B
5
GND
B
6
V
CC
B
7
B
8
B
9
B
10
B
11
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
memory is full or not. The IR and OR functions are selected in the First Word
Fall Through mode. IR indicates whether or not the FIFO has available memory
locations. OR shows whether the FIFO has data available for reading or not.
It marks the presence of valid data on the outputs.
Each FIFO has a programmable Almost-Empty flag (AEA and AEB) and
a programmable Almost-Full flag (AFA and AFB). AEA and AEB indicate
when a selected number of words remain in the FIFO memory. AFA and AFB
indicate when the FIFO contains more than a selected number of words.
FFA/IRA, FFB/IRB, AFA and AFB are two-stage synchronized to the
port clock that writes data into its array. EFA/ORA, EFB/ORB, AEA and AEB
are two-stage synchronized to the port clock that reads data from its array.
Programmable offsets for AEA, AEB, AFA and AFB are loaded by using
Port A. Three default offset settings are also provided. The AEA and AEB
threshold can be set at 8, 16 or 64 locations from the empty boundary and the
AFA and AFB threshold can be set at 8, 16 or 64 locations from the full boundary.
All these choices are made using the FS0 and FS1 inputs during Reset.
Two or more devices may be used in parallel to create wider data paths.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption (I
CC) is at a minimum. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
The IDT72V3652/72V3662/72V3672 are characterized for operation from
0°C to 70°C. Industrial temperature range (-40°C to +85°C) is available by
special order. They are fabricated using IDT’s high speed, submicron CMOS
technology.
NOTE:
1. Pin 1 identifier in corner.
