4
COMMERCIAL TEMPERATURE RANGE
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
FEBRUARY 4, 2009
Symbol Name I/O Description
A0-A35 Port A Data I/0 36-bit bidirectional data port for side A.
AEA Port A Almost- O Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is
Empty Flag (Port A) less than or equal to the value in the Almost-Empty A Offset register, X2.
AEB Port B Almost- O Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is
Empty Flag (Port B) less than or equal to the value in the Almost-Empty B Offset register, X1.
AFA Port A Almost- O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations in
Full Flag (Port A) FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.
AFB Port B Almost- O Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty locations in
Full Flag (Port B) FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2.
B0 - B35 Port B Data I/O 36-bit bidirectional data port for side B.
CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or
coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH
transition of CLKA.
CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through port Band can be asynchronous or
coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are synchronized to the LOW-to-HIGH
transition of CLKB.
CSA Port A Chip I CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write on port A. The A0-A35
Select outputs are in the high-impedance state when CSA is HIGH.
CSB Port B Chip I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The
Select B0- B35 outputs are in the high-impedance state when CSB is HIGH.
EFA/ORA Port A Empty/ O This is a dual function pin. In the IDT Standard mode, the EFA function is selected. EFA indicates
Output Ready whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA
Flag indicates the presence of valid data on A0-A35 outputs, available for reading. EFA/ORA is synchronized
to the LOW-to-HIGH transition of CLKA.
EFB/ORB Port B Empty/ O This is a dual function pin. In the IDT Standard mode, the EFB function is selected. EFB indicates
Output Ready whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB
Flag indicates the presence of valid data on B0-B35 outputs, available for reading. EFB/ORB is synchronized to
the LOW-to-HIGH transition of CLKB.
ENA Port A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB Port B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
FFA/IRA Port A Full/ O This is a dual function pin. In the IDT Standard mode, the FFA function is selected. FFA indicates
Input Ready whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA
Flag indicates whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is
synchronized to the LOW-to-HIGH transition of CLKA.
FFB/IRB Port B Full/ O This is a dual function pin. In the IDT Standard mode, the FFB function is selected. FFB indicates
Input Ready whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function is selected. IRB
Flag indicates whether or not there is space available for writing to the FIFO2 memory. FFB/IRB is
synchronized to the LOW-to-HIGH transition of CLKB.
FWFT First Word Fall I This pin selects the timing mode. A HIGH on FWFT selects IDT Standard mode, a LOW selects First
Through Mode Word Fall Through mode. Once the timing mode has been selected, the level on FWFT must be static
throughout device operation.
FS1, FS0 Flag Offset I
A LOW-to-HIGH transition of the FIFO Reset input latches the values of FS0 and FS1. If
either FS0 or
Selects
FS1 is HIGH when the FIFO Reset input goes HIGH, one of three preset
values is selected as the
offset for FIFOs Almost-Full and Almost-Empty flags. If both
FIFOs
are reset simultaneously and both
FS0 and FS1 are LOW when RST1 and RST2
go HIGH,
the first four writes to FIFO1 load the Almost-
Empty and Almost-Full offsets for both FIFOs.
PIN DESCRIPTIONS
