Figure 6. Port B Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
Figure 7. Port A Read Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
NOTE:
1.Read From FIFO2.
4660 drw08
CLKB
EFB/ORB
ENB
MBB
CSB
W/RB
t
CLK
t
CLKH
t
CLKL
t
A
t
MDV
t
EN
t
A
t
ENH
t
ENH
Previous Data
W1
W2
(1)(1)
t
ENH
t
DIS
No Operation
HIGH
t
A
t
MDV
t
EN
t
A
W1
W2
W3
(1)(1)(1)
t
DIS
B0-B35
(FWFT Mode)
B0-B35
(IDT Standard Mode)
OR
t
ENS2
t
ENS2
t
ENS2
CLKA
EFA/ORA
ENA
MBA
CSA
W/RA
t
CLK
t
CLKH
t
CLKL
t
ENH
t
ENH
t
ENH
No Operation
t
A
t
EN
t
A
W1
W2W3
(1)
(1)
(1)
t
DIS
A0-A35
(FWFT Mode)
t
EN
W2
(1)
(1)
t
DIS
W1Previous Data
A0-A35
(Standard Mode)
t
MDV
t
A
OR
t
A
t
MDV
4660 drw09
HIGH
t
ENS2
t
ENS2
t
ENS2
17
COMMERCIAL TEMPERATURE RANGE
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
FEBRUARY 4, 2009
NOTE:
1.tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
Figure 8. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
CSA
WRA
MBA
IRA
A0 - A35
CLKB
ORB
CSB
W/RB
MBB
ENA
ENB
B0 -B35
CLKA
4660 drw10
12
3
t
CLKH
t
CLKL
t
CLK
t
ENS2
t
ENS2
t
ENH
t
ENH
t
DS
t
DH
t
SKEW1
t
CLK
t
CLKL
t
POR
t
POR
t
ENS2
t
ENH
t
A
Old Data in FIFO1 Output RegisterW1
FIFO1Empty
LOW
HIGH
LOW
HIGH
LOW
t
CLKH
W1
HIGH
(1)
18
COMMERCIAL TEMPERATURE RANGE
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
FEBRUARY 4, 2009
NOTE:
1.tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Figure 9.
EFBEFB
EFBEFB
EFB
Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)
