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72V3672L15PF8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
7
COMMERCIAL TEMPERATURE RANGE
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
FEBRUARY 4, 2009
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3652/72V3662/72V3672 with
CLKA and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were
disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x ICC(f) + Σ(CL x VCC
2
X fo)
N
where:
N = number of outputs = 36
CL = output capacitance load
fo = switching frequency of an output
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
4660 drw03
A
35
A
34
A
33
A
32
V
CC
A
31
A
30
GND
A
29
A
28
A
27
A
26
A
25
A
24
A
23
FWFT
A
22
V
CC
A
21
A
20
A
19
A
18
GND
A
17
A
16
A
15
A
14
A
13
V
CC
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B
35
B
34
B
33
B
32
GND
B
31
B
30
B
29
B
28
B
27
B
26
V
CC
B
25
B
24
GND
B
23
B
22
B
21
B
20
B
19
B
18
GND
B
17
B
16
V
CC
B
15
B
14
B
13
B
12
GND
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
91
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
V
CC
GND
CLKA
ENA
W/RA
CSA
FFA/IRA
EFA/ORA
VCC
AFA
AEA
MBF2
MBA
RST1
FS0
GND
FS1
RST2
MBB
MBF1
V
CC
AEB
AFB
EFB/ORB
FFB/IRB
GND
CSB
W/RB
ENB
CLKB
GND
A11
A10
A9
A8
A7
A6
GND
A
5
A4
A3
VCC
A2
A1
A0
GND
B
0
B1
B2
B3
B4
B5
GND
B
6
VCC
B7
B8
B9
B10
B11
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
8
COMMERCIAL TEMPERATURE RANGE
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
FEBRUARY 4, 2009
IDT72V3652L10
(1)
IDT72V3652L15
IDT72V3662L10
(1)
IDT72V3662L15
IDT72V3672L10
(1)
IDT72V3672L15
Symbol Parameter Min. Max. Min. Max. Unit
f
S Clock Frequency, CLKA or CLKB — 100 — 66.7 MHz
tCLK Clock Cycle Time, CLKA or CLKB 10 — 15 — ns
t
CLKH Pulse Duration, CLKA or CLKB HIGH 4.5 — 6 — ns
t
CLKL Pulse Duration, CLKA and CLKB LOW 4.5 — 6 — ns
tDS Setup Time, A0-A35 before CLKA↑ and B0-B35 3 — 4 — ns
before CLKB↑
t
ENS1 Setup Time, CSA and W/RA, before 4 — 4.5 — ns
CLKA↑; CSB, and W/RB before CLKB↑
tENS2 Setup Time, ENA and MBA, before 3 — 4.5 — ns
CLKA↑; ENB, and MBB before CLKB↑
tRSTS Setup Time, RST1 or RST2 LOW before CLKA↑ 5—5—ns
or CLKB↑
(2)
tFSS Setup Time, FS0 and FS1 before RST1 and RST2 HIGH 7.5 — 7.5 — ns
tFWS Setup Time, FWFT before CLKA↑ 0—0—ns
tDH Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑ 0.5 — 1 — ns
tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; 0.5 — 1 — ns
CSB, W/RB, ENB, and MBB after CLKB↑
tRSTH Hold Time, RST1 or RST2 LOW after CLKA↑ or CLKB↑
(2)
4—4—ns
tFSH Hold Time, FS0 and FS1 after RST1 and RST2 HIGH 2 — 2 — ns
tSKEW1
(3)
Skew Time, between CLKA↑ and CLKB↑ for EFA/ORA, 7.5 — 7.5 — ns
EFB/ORB, FFA/IRA, and FFB/IRB
tSKEW2
(3,4)
Skew Time, between CLKA↑ and CLKB↑ for AEA,12—12—ns
AEB, AFA, and AFB
NOTES:
1. For 10ns speed grade:
Vcc = 3.3V ± 0.15V; TA = 0° to +70°.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3.
Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(For 10ns speed grade only: Vcc = 3.3V ± 0.15V; TA = 0°C to +70°C; JEDEC JESD8-A compliant)
9
COMMERCIAL TEMPERATURE RANGE
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
FEBRUARY 4, 2009
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 pF
IDT72V3652L10
(1)
IDT72V3652L15
IDT72V3662L10
(1)
IDT72V3662L15
IDT72V3672L10
(1)
IDT72V3672L15
Symbol Parameter Min. Max. Min. Max. Unit
tA Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35 2 6.5 2 10 ns
tPIR Propagation Delay Time, CLKA↑ to FFA/IRA and CLKB↑ to 2 6.5 2 8 ns
FFB/IRB
t
POR Propagation Delay Time, CLKA↑ to EFA/ORA and CLKB↑ to 1 6.5 1 8 ns
EFB/ORB
t
PAE Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB 1 6.5 1 8 ns
tPAF Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB 1 6.5 1 8 ns
t
PMF Propagation Delay Time, CLKA↑ to MBF1 LOW or 0 6.5 0 8 ns
MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH
t
PMR Propagation Delay Time, CLKA↑ to B0-B35
(2)
and 2 8 2 10 ns
CLKB↑ to A0-A35
(3)
tMDV Propagation Delay Time, MBA to A0-A35 valid and 2 6.5 2 10 ns
MBB to B0-B35 Valid
tPRF Propagation Delay Time, RST1 LOW to AEB LOW, AFA 110 115ns
HIGH, and MBF1 HIGH, and RST2 LOW to AEA LOW,
AFB HIGH, and MBF2 HIGH
tEN Enable Time, CSA and W/RA LOW to A0-A35 Active 2 6 2 10 ns
and CSB LOW and W/RB HIGH to B0-B35 Active
tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance 1 6 1 8 ns
and CSB HIGH or W/RB LOW to B0-B35 at high-impedance
NOTES:
1. For 10ns speed grade:
Vcc = 3.3V ± 0.15V; TA = 0° to +70°.
2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
(For 10ns speed grade only: Vcc = 3.3V ± 0.15V; TA = 0°C to +70°C; JEDEC JESD8-A compliant)
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72V3672L15PF8

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IC FIFO 16384X36 15NS 120QFP
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