1.tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
cycle later than shown.
Figure 10. ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty (FWFT Mode)
CSB
W/RB
MBB
IRB
B0 - B35
CLKA
ORA
CSA
W/RA
MBA
ENB
ENA
A0 -A35
CLKB
4660 drw12
12
3
t
CLKH
t
CLKL
t
CLK
t
ENS2
t
ENS2
t
ENH
t
ENH
t
DS
t
DH
t
SKEW1
t
CLK
t
CLKH
t
POR
t
POR
t
ENS2
t
ENH
t
A
Old Data in FIFO2 Output RegisterW1
FIFO2 Empty
t
CLKL
LOW
LOW
LOW
LOW
LOW
HIGH
W1
(1)
20
COMMERCIAL TEMPERATURE RANGE
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
FEBRUARY 4, 2009
NOTE:
1.tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
Figure 11.
EFAEFA
EFAEFA
EFA
Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)
CSB
W/RB
MBB
FFB
B0-B35
CLKA
EFA
CSA
W/RA
MBA
ENB
ENA
A0-A35
CLKB
12
4660 drw13
tCLKH
tCLKL
tCLK
tENS2
tENS2
tENH
tENH
tDS
tDH
tSKEW1
(1)
tCLK
tCLKL
tENS2
tENH
tA
W1
FIFO2 Empty
LOW
LOW
LOW
LOW
LOW
tCLKH
W1
HIGH
tPORtPOR
21
COMMERCIAL TEMPERATURE RANGE
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
FEBRUARY 4, 2009
NOTE:
1.tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
Figure 12. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
