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TDA8034AT/C1,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
TDA8034T_TDA8034AT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3.1 — 13 December 2012 10 of 30
NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
8.7 Deactivation sequence
When a session ends, the microcontroller sets pin CMDVCCN HIGH. The
TDA8034T/TDA8034AT then executes an automatic deactivation sequence by counting
the sequencer back to the inactive state (see Figure 7
) as follows:
1. Pin RST is pulled LOW (t11).
2. The clock is stopped, pin CLK is LOW (t12).
3. Pin I/O is pulled LOW (t13).
4. V
CC
falls to 0 V (t14). The deactivation sequence is completed when V
CC
reaches its
inactive state.
5. V
CC
< 0.4 V (t
deac
)
6. All card contacts become low-impedance to GND. However, pin I/OUC remains pulled
up to V
DD
using the 11 k resistor.
7. The internal oscillator returns to its low frequency mode.
Calculation of the time delays is as follows:
• t11 = t10 + 3T / 64
• t12 = t11 + T / 2
• t13 = t11 + T
• t14 = t11 + 3T / 2
• t
deac
= t11 + 3T / 2 + V
CC
fall time
OSCINT = internal oscillator.
Fig 6. Activation sequence at t3
001aai966
CMDVCCN
XTAL
V
CC
I/O ATR
CLK
> 200 ns
RSTIN
RST
I/OUC
OSCINT
t0 t
d(end)
= t
act
t1 = t2
t
d(start)
t4
low frequency high frequency
TDA8034T_TDA8034AT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3.1 — 13 December 2012 11 of 30
NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
Remark: The value of period T is 64 times the period interval of the internal oscillator (i.e.
25 s).
8.8 V
CC
regulator
The V
CC
buffer is able to continuously deliver up to 65 mA at V
CC
= 5V or 3V.
The V
CC
buffer has an internal overload protection with a threshold value of approximately
120 mA. This detection is internally filtered, enabling spurious current pulses up to
200 mA with a duration of a few milliseconds to be drawn by the card without causing
deactivation. However, the average current value must stay below maximum; see Table 8
.
8.9 Fault detection
The following conditions are monitored by the fault detection circuit:
• Short-circuit or high current on pin V
CC
• Card removal during transaction
• V
DDP
falling
• V
DD
falling
• V
DD(INTF)
falling
• Overheating
Fault detection monitors two different situations:
• Outside card sessions, pin CMDVCCN is HIGH: pin OFFN is LOW if the card is not in
the reader and HIGH if the card is in the reader. Any voltage drop on V
DD
is detected
by the voltage supervisor. This generates an internal power-on reset pulse but does
not act upon the pin OFFN signal. The card is not powered-up and short-circuits or
overheating are not detected.
OSCINT = internal oscillator.
Fig 7. Deactivation sequence
001aak995
RST
CLK
I/O
V
CC
XTAL1
OSCINT
CMDVCC
high frequency
t10 t11 t12 t13
t
deact
t14
low frequency
TDA8034T_TDA8034AT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3.1 — 13 December 2012 12 of 30
NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
• In card sessions, pin CMDVCCN is LOW: when pin OFFN goes LOW, the fault
detection circuit triggers the automatic emergency deactivation sequence (see
Figure 8
). When the microcontroller resets pin CMDVCCN to HIGH, after the
deactivation sequence, pin OFFN is rechecked. If the card is still present, pin OFFN
returns to HIGH. This check identifies the fault as either a hardware problem or a card
removal incident.
On card insertion or removal, bouncing can occur in the PRESN signal. This depends on
the type of card presence switch in the connector (normally open or normally closed) and
the mechanical characteristics of the switch. To correct for this, a debouncing feature is
integrated in to the TDA8034T/TDA8034AT. This feature operates at a typical duration of
4.5 ms (t
deb
= 640 (
1
⁄
fosc(int)low
). Figure 9 on page 13 shows the operation of the
debouncing feature.
On card insertion, pin OFFN goes HIGH after the debounce time has elapsed. When the
card is extracted, the automatic card deactivation sequence is performed on the first
HIGH/LOW transition on pin PRESN. After this, pin OFFN goes LOW.
Fig 8. Emergency deactivation sequence after card removal
001aai971
OFFN
PRESN
CLK
I/O
V
CC
XTAL
OSCINT
t10 t12
t
deact
t13
t14
RST
low frequencyhigh frequency
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

TDA8034AT/C1,112

Mfr. #:
Buy TDA8034AT/C1,112
Manufacturer:
NXP Semiconductors
Description:
Interface - Specialized SMART CARD INTERFACE
Lifecycle:
New from this manufacturer.
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