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TDA8034AT/C1,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
TDA8034T_TDA8034AT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3.1 — 13 December 2012 7 of 30
NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
8.3 Clock circuits
The clock signal from pin CLK to the card is either supplied by an external clock signal
connected to pin XTAL1 or generated using a crystal connected between pins XTAL1 and
XTAL2. The TDA8034T/TDA8034AT automatically detects if an external clock is
connected to XTAL1, eliminating the need for a separate pin to select the clock source.
Automatic clock source detection is performed on each activation command (falling edge
of the signal on pin CMDVCCN). The presence of an external clock on pin XTAL1 is
checked during a time window defined by the internal oscillator. If a clock is detected, the
internal crystal oscillator is stopped. If a clock is not detected, the internal crystal oscillator
is started. When an external clock is used, it is mandatory that the clock is applied to pin
XTAL1 before the falling edge of the signal on pin CMDVCCN.
The clock frequency is selected using pin CLKDIV1 to be either
1
⁄
2
f
xtal
or
1
⁄
4
f
xtal
on
TDA8034T or f
xtal
or
1
⁄
2
f
xtal
on TDA8034AT as shown in Table 4.
The frequency change is synchronous and as such during transition, no pulse is shorter
than 45 % of the smallest period. In addition, only the first and last clock pulse around the
change has the correct width. When dynamically changing the frequency, the modification
is only effective after 10 clock periods on pin XTAL1.
The duty cycle of f
xtal
on pin CLK should be between 45 % and 55 %. If an external clock
is connected to pin XTAL1, its duty cycle must be between 48 % and 52 %.
When the frequency of the clock signal on pin CLK is either
1
⁄
2
f
xtal
or
1
⁄
4
f
xtal
on TDA8034T
or f
xtal
or
1
⁄
2
f
xtal
on TDA8034AT, the frequency dividers guarantee a duty cycle between
45 % and 55 %.
enclkin and clkxtal are internal signal names.
Fig 5. Basic layout for using an external clock
Table 4. Clock configuration
Pin CLKDIV1 level Pin CLK level
TDA8034T TDA8034AT
HIGH
1
⁄
2
f
xtal
1
⁄
2
f
xtal
LOW
1
⁄
4
f
xtal
f
xtal
001aak992
DIGITAL
MULTIPLEXER
CRYSTAL
XTAL1 XTAL2
clkxtalenclkin
TDA8034T_TDA8034AT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3.1 — 13 December 2012 8 of 30
NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
8.4 Input and output circuits
When pins I/O and I/OUC are pulled HIGH using an 11 k resistor between pins I/O and
V
CC
and/or between pins I/OUC and V
DD(INTF)
, both lines enter the idle state. Pin I/O is
referenced to V
CC
and pin I/OUC to V
DD(INTF)
, thus allowing operation at V
CC
V
DD(INTF)
.
The first side on which a falling edge occurs becomes the master. An anti-latch circuit
disables falling edge detection on the other line, making it the slave. After a time delay t
d
,
the logic 0 present on the master-side is sent to the slave-side. When the master-side
returns logic 1, the slave-side sends logic 1 during time delay (t
w(pu)
). After this sequence,
both master and slave sides return to their idle states.
The active pull-up feature ensures fast LOW-to-HIGH transitions making the
TDA8034T/TDA8034AT capable of delivering more than 1 mA, up to an output voltage of
0.9V
CC
, at a load of 80 pF. At the end of the active pull-up pulse, the output voltage is
dependent on the internal pull-up resistor value and load current. The current sent to and
received from the card’s I/O lines is limited to 15 mA at a maximum frequency of 1 MHz.
TDA8034T_TDA8034AT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3.1 — 13 December 2012 9 of 30
NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
8.5 Shutdown mode
After a power-on reset, if pin CMDVCCN is HIGH, the circuit enters the Shutdown mode,
ensuring only the minimum number of circuits are active while the TDA8034T/TDA8034AT
waits for the microcontroller to start a session.
• all card contacts are inactive. The impedance between the contacts and GND is
approximately 200 .
• pin I/OUC is high-impedance using the 11 k pull-up resistor connected to V
DD(INTF)
• the voltage generators are stopped
• the voltage supervisor is active
• the internal oscillator runs at its lowest frequency (f
osc(int)low
)
8.6 Activation sequence
The following device activation sequence is applied when using an external clock; see
Figure 6
:
1. Pin CMDVCCN is pulled LOW (t0).
2. The internal oscillator is triggered (t0).
3. The internal oscillator changes to high frequency (t1).
4. V
CC
rises from either 0 V to 3 V or 0 V to 5 V on a controlled slope (t2).
5. Pin I/O is driven HIGH (t3).
6. The clock on pin CLK is applied to the C3 contact (t4).
7. Pin RST is enabled (t5).
Calculation of the time delays is as follows:
• t1 = t0 + 384
1
⁄
fosc(int)low
• t2 = t1
• t3 = t1 + 17T / 2
• t4 = driven by host controller; > t3 and < t5
• t5 = t1 + 23T / 2
Remark: The value of period T is 64 times the period interval of the internal oscillator at
high frequency (
1
⁄
fosc(int)high
); t3 is called t
d(start)
and t5 is called t
d(end)
.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

TDA8034AT/C1,112

Mfr. #:
Buy TDA8034AT/C1,112
Manufacturer:
NXP Semiconductors
Description:
Interface - Specialized SMART CARD INTERFACE
Lifecycle:
New from this manufacturer.
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