AD7678ASTZ Datasheet AD7678ASTZRL, AD7678ACPZ, AD7678ACPZRL | P19-P21

AD7678

Rev. A | Page 18 of 28

The AD8021 meets these requirements and is usually appropri-

ate for almost all applications. The AD8021 needs a 10 pF

external compensation capacitor, which should have good

linearity as an NPO ceramic or mica type.

The AD8022 could be used if a dual version is needed and gain

of 1 is present. The AD829 is an alternative in applications

where high frequency (above 100 kHz) performance is not

required. In gain of 1 applications, it requires an 82 pF

compensation capacitor. The AD8610 is another option when

low bias current is needed in low frequency applications.

Single-to-Differential Driver

For applications using unipolar analog signals, a single-ended-

to-differential driver will allow for a differential input into the

part. The schematic is shown in Figure 24. When provided an

input signal of 0 to V

REF

, this configuration will produce a

differential ±V

REF

with midscale at V

REF

/2.

If the application can tolerate more noise, the AD8138

differential driver can be used.

8.25k



2.5V

AD8021

590



AD7678

IN+

IN–

REF

ANALOG INPUT

(UNIPOLAR

0V TO 4.096V)

10pF

AD8021

590



10pF



100nF

1.82k



REFBUFIN

03084-0-030

Figure 24. Single-Ended-to-Differential Driver Circuit

(Internal Reference Buffer Used)

Voltage Reference

The AD7678 allows the use of an external voltage reference with

or without the internal reference buffer.

Using the internal reference buffer is recommended when

sharing a common reference voltage between multiple ADCs is

desired.

However, the advantages of using the external reference voltage

directly are



The SNR and dynamic range improvement (about 1.7 dB)

resulting from the use of a reference voltage very close to

the supply (5 V) instead of a typical 4.096 V reference

when the internal buffer is used.



The power saving when the internal reference buffer is

powered down (PDBUF HIGH).

To use the internal reference buffer, PDBUF should be LOW. A

2.5 V reference voltage applied on the REFBUFIN input will

result in a 4.096 V reference on the REF pin.

In both cases, the voltage reference input REF has a dynamic

input impedance and therefore requires an efficient decoupling

between REF and REFGND inputs. The decoupling consists of

a low ESR 47 μF tantalum capacitor connected to the REF and

REFGND inputs with minimum parasitic inductance.

Care should also be taken with the reference temperature

coefficient of the voltage reference, which directly affects the

full-scale accuracy if this parameter matters. For instance, a

±4 ppm/°C temperature coefficient of the reference changes the

full scale by ±1 LSB/°C.

Power Supply

The AD7678 uses three sets of power supply pins: an analog 5 V

supply (AVDD), a digital 5 V core supply (DVDD), and a digital

output interface supply (OVDD). The OVDD supply defines

the output logic level and allows direct interface with any logic

working between 2.7 V and DVDD + 0.3 V. To reduce the

number of supplies needed, the digital core (DVDD) can be

supplied through a simple RC filter from the analog supply, as

shown in Figure 21. The AD7678 is independent of power

supply sequencing once OVDD does not exceed DVDD by

more than 0.3 V, and is therefore free from supply voltage

induced latch-up. Additionally, it is very insensitive to power

supply variations over a wide frequency range, as shown in

Figure 25.

FREQUECY (kHz)

PSRR (dB)

100 1000 10000110

03084-0-031

Figure 25. PSRR vs. Frequency

AD7678

Rev. A | Page 19 of 28

POWER DISSIPATION VERSUS THROUGHPUT

The AD7678 automatically reduces its power consumption at

the end of each conversion phase. During the acquisition phase,

the operating currents are very low, which allows for a signifi-

cant power savings when the conversion rate is reduced, as

shown in Figure 26. This feature makes the AD7678 ideal for

very low power battery applications.

It should be noted that the digital interface remains active even

during the acquisition phase. To reduce the operating digital

supply currents even further, the digital inputs need to be

driven close to the power rails (DVDD and DGND), and

OVDD should not exceed DVDD by more than 0.3 V.

SAMPLING RATE (SPS)

POWER DISSIPATION (mW)

100000

10000

1000

100

0.1

100

10k1k1001

PDBUF HIGH

03084-0-032

Figure 26. Power Dissipation vs. Sample Rate

CONVERSION CONTROL

Figure 27 shows the detailed timing diagrams of the conversion

process. The AD7678 is controlled by the

CNVST

signal, which

initiates conversion. Once initiated, it cannot be restarted or

aborted, even by the power-down input PD, until the

conversion is complete. The

CNVST

signal operates

independently of the

and

signals.

CNVST

MODE ACQUIRE CONVERT ACQUIRE CONVERT

BUSY

03084-0-033

Figure 27. Basic Conversion Timing

Although

CNVST

is a digital signal, it should be designed with

special care with fast, clean edges and levels with minimum

overshoot and undershoot or ringing.

For other applications, conversions can be automatically

initiated. If

CNVST

is held low when BUSY is low, the AD7678

controls the acquisition phase and then automatically initiates a

new conversion. By keeping

CNVST

low, the AD7678 keeps the

conversion process running by itself. It should be noted that the

analog input has to be settled when BUSY goes low. Also, at

power-up,

CNVST

should be brought low once to initiate the

conversion process. In this mode, the AD7678 could sometimes

run slightly faster than the guaranteed limits of 100 kSPS.

RESET

DATA

BUS

BUSY

CNVST

03084-0-034

Figure 28. RESET Timing

AD7678

Rev. A | Page 20 of 28

DIGITAL INTERFACE

The AD7678 has a versatile digital interface; it can be interfaced

with the host system by using either a serial or parallel interface.

The serial interface is multiplexed on the parallel data bus. The

AD7678 digital interface also accommodates both 3 V and 5 V

logic by simply connecting the AD7678’s OVDD supply pin to

the host system interface digital supply. Finally, by using the

OB/

input pin in any mode except 18-bit interface mode,

both twos complement and straight binary coding can be used.

The two signals,

and

, control the interface. When at least

one of these signals is high, the interface outputs are in high

impedance. Usually,

allows the selection of each AD7678 in

multicircuit applications, and is held low in a single AD7678

design.

is generally used to enable the conversion result on

the data bus.

CNVST

BUSY

DATA

BUS

CS = RD = 0

PREVIOUS CONVERSION DATA NEW DATA

03084-0-035

Figure 29. Master Parallel Data Timing for Reading (Continuous Read)

PARALLEL INTERFACE

The AD7678 is configured to use the parallel interface with an

18-bit, a 16-bit, or an 8-bit bus width, according to Table 7. The

data can be read either after each conversion, which is during

the next acquisition phase, or during the following conversion,

as shown in Figure 30 and Figure 31, respectively. When the

data is read during the conversion, however, it is recommended

that it is read only during the first half of the conversion phase.

This avoids any potential feedthrough between voltage

transients on the digital interface and the most critical analog

conversion circuitry. Refer to Table 7 for a detailed description

of the different options available.

DATA

BUS

BUSY

CURRENT

CONVERSION

03084-0-036

Figure 30. Slave Parallel Data Timing for Reading (Read after Convert)

CS = 0

CNVST,

CONVERSION

DATA

BUS

BUSY

03084-0-037

Figure 31. Slave Parallel Data Timing for Reading (Read during Convert)

A0, A1

PINS D[15:8]

PINS D[7:0]

HI-Z

HIGH BYTE LOW BYTE

LOW BYTE HIGH BYTE

HI-Z

03084-0-038

Figure 32. 8-Bit and 16-Bit Parallel Interface

SERIAL INTERFACE

The AD7678 is configured to use the serial interface when

MODE0 and MODE1 are held high. The AD7678 outputs 18

bits of data, MSB first, on the SDOUT pin. This data is

synchronized with the 18 clock pulses provided on the SCLK

pin. The output data is valid on both the rising and falling edge

of the data clock.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

AD7678ASTZ

Mfr. #:

Buy AD7678ASTZ

Manufacturer:

Description:

Analog to Digital Converters - ADC IC 18-Bit 100 kSPS

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AD7678ASTZ

AD7678ASTZ

Products related to this Datasheet