AD7678
Rev. A | Page 24 of 28
BUSY BUSY
AD7678
#2 (UPSTREAM)
AD7678
#1 (DOWNSTREAM)
RDC/SDIN SDOUT
CNVST
CS
SCLK
RDC/SDIN SDOUT
CNVST
CS
SCLK
DATA
OUT
SCLK IN
CS IN
CNVST IN
BUSY
OUT
03084-0-043
Figure 37. Two AD7678s in a Daisy-Chain Configuration
External Clock Data Read during Conversion
Figure 36 shows the detailed timing diagrams of this method.
During a conversion, while both
CS
and
RD
are low, the result
of the previous conversion can be read. The data is shifted out
MSB first with 18 clock pulses, and is valid on both the rising
and falling edge of the clock. The 18 bits have to be read before
the current conversion is complete. If that is not done,
RDERROR is pulsed high and can be used to interrupt the host
interface to prevent incomplete data reading. There is no daisy-
chain feature in this mode, and the RDC/SDIN input should
always be tied either high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock is recommended to ensure that all bits are
read during the first half of the conversion phase. It is also
possible to begin to read the data after conversion and continue
to read the last bits even after a new conversion has been
initiated.
MICROPROCESSOR INTERFACING
The AD7678 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and for ac signal
processing applications interfacing to a digital signal processor.
The AD7678 is designed to interface either with a parallel 8-bit
or 16-bit wide interface, or with a general-purpose serial port or
I/O ports on a microcontroller. A variety of external buffers can
be used with the AD7678 to prevent digital noise from coupling
into the ADC. The following section illustrates the use of the
AD7678 with an SPI equipped DSP, the ADSP-219x.
SPI Interface (ADSP-219x)
Figure 38 shows an interface diagram between the AD7678 and
the SPI equipped ADSP-219x. To accommodate the slower
speed of the DSP, the AD7678 acts as a slave device, and data
must be read after conversion. This mode also allows the daisy-
chain feature. The convert command could be initiated in
response to an internal timer interrupt. The 18-bit output data
are read with 3-byte SPI access. The reading process could be
initiated in response to the end-of-conversion signal (BUSY
going low) using an interrupt line of the DSP. The serial
interface (SPI) on the ADSP-219x is configured for master
mode (MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase
bit (CPHA) = 1, and SPI interrupt enable (TIMOD) = 00, by
writing to the SPI control register (SPICLTx). It should be noted
that to meet all timing requirements, the SPI clock should be
limited to 17 Mbits/s, which allow it to read an ADC result in
about 1.1 μs.
AD7678*
ADSP-219x*
SER/PAR
PFx
MISOx
SCKx
PFx or TFSx
BUSY
SDOUT
SCLK
CNVST
EXT/INT
CS
RD
INVSCLK
DVDD
*ADDITIONAL PINS OMITTED FOR CLARITY
SPIxSEL (PFx)
03084-0-044
Figure 38. Interfacing the AD7678 to an SPI Interface
AD7678
Rev. A | Page 25 of 28
APPLICATION HINTS
LAYOUT
The AD7678 has very good immunity to noise on the power
supplies. However, care should still be taken with regard to
grounding layout.
The printed circuit board that houses the AD7678 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. Digital and
analog ground planes should be joined in only one place,
preferably underneath the AD7678, or at least as close to the
AD7678 as possible. If the AD7678 is in a system where
multiple devices require analog-to-digital ground connections,
the connection should still be made at one point only, a star
ground point that should be established as close to the AD7678
as possible.
The user should avoid running digital lines under the device,
because these will couple noise onto the die. The analog ground
plane should be allowed to run under the AD7678 to avoid
noise coupling. Fast switching signals like
CNVST
or clocks
should be shielded with digital ground to avoid radiating noise
to other sections of the board, and should never run near
analog signal paths. Crossover of digital and analog signals
should be avoided. Traces on different but close layers of the
board should run at right angles to each other. This will reduce
the effect of feedthrough through the board. The power supply
lines to the AD7678 should use as large a trace as possible to
provide low impedance paths and reduce the effect of glitches
on the power supply lines. Good decoupling is also important
to lower the supply’s impedance presented to the AD7678 and
to reduce the magnitude of the supply spikes. Decoupling
ceramic capacitors, typically 100 nF, should be placed close to
and ideally right up against each power supply pin (AVDD,
DVDD, and OVDD) and their corresponding ground pins.
Additionally, low ESR 10 μF capacitors should be located near
the ADC to further reduce low frequency ripple.
The DVDD supply of the AD7678 can be a separate supply or
can come from the analog supply, AVDD, or the digital
interface supply, OVDD. When the system digital supply is
noisy or when fast switching digital signals are present, and if
no separate supply is available, the user should connect the
DVDD digital supply to the analog supply AVDD through an
RC filter (see Figure 21), and connect the system supply to the
interface digital supply OVDD and the remaining digital
circuitry. When DVDD is powered from the system supply, it is
useful to insert a bead to further reduce high frequency spikes.
The AD7678 has four different ground pins: REFGND, AGND,
DGND, and OGND. REFGND senses the reference voltage and
should be a low impedance return to the reference because it
carries pulsed currents. AGND is the ground to which most
internal ADC analog signals are referenced. This ground must
be connected with the least resistance to the analog ground
plane. DGND must be tied to the analog or digital ground plane
depending on the configuration. OGND is connected to the
digital system ground.
The layout of the decoupling of the reference voltage is
important. The decoupling capacitor should be close to the
ADC and should be connected with short and large traces to
minimize parasitic inductances.
EVALUATING THE AD7678’S PERFORMANCE
The evaluation board for the AD7678 allows a quick means to
measure both dc (histograms and time domain) and ac (time
and frequency domain) performances of the converter. The
EVAL-AD7678CBZ is an evaluation board package that includes
a fully assembled and tested evaluation board, documentation,
and software. The accompanying software requires the use of a
capture board that must be ordered seperately from the evalua-
tion board (see the Ordering Guide for information). The
evaluation board can also be used in a standalone configuration
and does not use the software when in this mode. Refer to the
EVAL-AD76XXEDZ and EVAL-AD76XXCBZ data sheets
available from www.analog.com for evaluation board details.
Two types of data capture boards can be used with the EVAL-
AD7678CBZ:
USB based (EVAL-CED1Z recommended)
Parallel port based (EVAL-CONTROL BRD3Z not
recommended because many newer PCs do not include
parallel ports any longer)
The recommended board layout for the AD7678 is outlined in
the evaluation board data sheet.
AD7678
Rev. A | Page 26 of 28
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
TOP VIEW
(PINS DOWN)
1
12
13
25
24
36
37
48
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
1.60
MAX
0.75
0.60
0.45
VIEW A
PIN 1
0.20
0.09
1.45
1.40
1.35
0.08
COPLANARITY
VIEW A
ROTATED 90° CCW
SEATING
PLANE
3.5°
0.15
0.05
9.20
9.00 SQ
8.80
7.20
7.00 SQ
6.80
051706-A
Figure 39. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
PIN 1
INDICATOR
TOP
VIEW
6.75
BSC SQ
7.00
BSC SQ
1
48
12
13
37
36
24
25
5.25
5.10 SQ
4.95
0.50
0.40
0.30
0.30
0.23
0.18
0.50 BSC
12° MAX
0.20 REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
5.50
REF
0.05 MAX
0.02 NOM
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
COPLANARITY
0.08
SEATING
PLANE
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
080108-A
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 40. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad (CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD7678ASTZ
1
–40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48
AD7678ASTZRL
1
–40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48
AD7678ACPZ
1
–40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1
AD7678ACPZRL
1
–40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1
EVAL-AD7678CBZ
2
Evaluation Board
EVAL-CONTROL BRD2Z
1, 3
Parallel Port Capture Board, 32k RAM
EVAL-CONTROL BRD3Z
1, 3
Parallel Port Capture Board, 128k RAM
EVAL-CED1Z
1, 3
USB Data Capture Board
1
Z = RoHS Compliant Part.
2
This board can be used as a standalone evaluation board or in conjunction with the a capture board for evaluation/demonstration purposes.
3
These capture board allow the PC to control and communicate with all Analog Devices evaluation boards ending in ED for EVAL-CED1Z and CB for EVAL-CONTROL
BRDxZ (x = 2, 3).

AD7678ASTZ

Mfr. #:
Manufacturer:
Description:
Analog to Digital Converters - ADC IC 18-Bit 100 kSPS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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