AD7678ASTZ Datasheet AD7678ASTZRL, AD7678ACPZ, AD7678ACPZRL | P7-P9

AD7678

Rev. A | Page 6 of 28

Table 4. Serial Clock Timings in Master Read after Convert

DIVSCLK[1] 0 0 1 1

Unit

DIVSCLK[0] Symbol 0 1 0 1

SYNC to SCLK First Edge Delay Minimum t

3 17 17 17 ns

Internal SCLK Period Minimum t

25 60 120 240 ns

Internal SCLK Period Maximum t

40 80 160 320 ns

Internal SCLK HIGH Minimum t

12 22 50 100 ns

Internal SCLK LOW Minimum t

7 21 49 99 ns

SDOUT Valid Setup Time Minimum t

4 18 18 18 ns

SDOUT Valid Hold Time Minimum t

2 4 30 89 ns

SCLK Last Edge to SYNC Delay Minimum t

3 60 140 300 ns

Busy High Width Maximum t

2.25 3 4.5 7.5 μs

AD7678

Rev. A | Page 7 of 28

ABSOLUTE MAXIMUM RATINGS

Table 5. AD7678 Absolute Maximum Ratings

Parameter Rating

Analog Inputs

IN+

, IN–

, REF, REFBUFIN, REFGND

to AGND

AVDD + 0.3 V to

AGND – 0.3 V

Ground Voltage Differences

AGND, DGND, OGND ±0.3 V

Supply Voltages

AVDD, DVDD, OVDD –0.3 V to +7 V

AVDD to DVDD, AVDD to OVDD ±7 V

DVDD to OVDD –0.3 V to +7 V

Digital Inputs –0.3 V to DVDD + 0.3 V

Internal Power Dissipation

700 mW

Internal Power Dissipation

2.5 W

Junction Temperature 150°C

Storage Temperature Range –65°C to +150°C

Lead Temperature Range

(Soldering 10 sec)

300°C

Stresses above those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional

operation of the device at these or any other conditions above those

indicated in the operational section of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may

affect device reliability.

See Analog Inputs section.

Specification is for device in free air: 48-Lead LQFP: θ

= 91°C/W,

= 30°C/W.

Specification is for device in free air: 48-Lead LFCSP: θ

= 26°C/W.

TO OUTPUT

60pF

500A

1.6mA

1.4V

IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND

SDOUT TIMINGS ARE DEFINEDWITH A MAXIMUM LOAD

OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.

03084–0–002

Figure 2. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, SCLK Outputs, C

= 10 pF

0.8V

DELAY

0.8V

DELAY

03084–0–003

Figure 3. Voltage Reference Levels for Timing

ESD CAUTION

AD7678

Rev. A | Page 8 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 39 38 3743 42 41 40

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

AGND

CNVST

RESET

DGND

AGND

AV D D

MODE0

MODE1

D0/OB/2C

D1/A0

D2/A1

D4/DIVSCLK[0]

BUSY

D17

D16

D15

AD7678

D5/DIVSCLK[1]

D14

PDBUF

AVDD

REFBUFIN

AGND

IN+

IN–

REFGND

REF

D6/EXT/INT

D7/INVSYNC

D8/INVSCLK

D9/RDC/SDIN

OGND

OVDD

DVDD

DGND

D10/SDOUT

D11/SCLK

D12/SYNC

D13/RDERROR

03084-004

NOTES

1. NC = NO CONNECT.

. THE EXPOSED PAD IS INTERNALLY CONNECTED TO AGND. THIS

CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICA

PERFORMANCES; HOWEVER, FOR INCREASED RELIABILITY O

THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE

SOLDERED TO THE ANALOG GROUND OF THE SYSTEM.

Figure 4. 48-Lead LQFP and 48-Lead LFCSP (ST-48 and CP-48) Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type

Description

1, 44 AGND P Analog Power Ground Pin.

2, 47 AVDD P Input Analog Power Pins. Nominally 5 V.

3 MODE0 DI Data Output Interface Mode Selection.

4 MODE1 DI Data Output Interface Mode Selection:

Interface MODE # MODE1 MODE0 Description

0 0 0 18-Bit Interface

1 0 1 16-Bit Interface

2 1 0 Byte Interface

3 1 1 Serial Interface

D0/OB/2C

DI/O

When MODE = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the

data coding is straight binary. In all other modes, this pin allows choice of straight binary/binary twos

complement. When OB/2C

is HIGH, the digital output is straight binary; when LOW, the MSB is

inverted, resulting in a twos complement output from its internal shift register.

6, 7,

40–42,

NC No Connect.

8 D1/A0 DI/O

When MODE = 0 (18-bit interface mode), this pin is Bit 1 of the parallel port data output bus. In all

other modes, this input pin controls the form in which data is output, as shown in Table 7.

9 D2/A1 DI/O

When MODE = 0 or 1 (18-bit or 16-bit interface mode), this pin is Bit 2 of the parallel port data output

bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7.

10 D3 DO

In all modes except MODE = 3, this output is used as Bit 3 of the parallel port data output bus. This pin

is always an output, regardless of the interface mode.

11, 12 D[4:5]or

DIVSCLK[0:1]

DI/O In all modes except MODE = 3, these pins are Bit 4 and Bit 5 of the parallel port data output bus.

When MODE = 3 (serial mode), EXT/INT

is LOW, and RDC/SDIN is LOW (serial master read after

convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock

that clocks the data output. In other serial modes, these pins are not used.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

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