AD7678
Rev. A | Page 22 of 28
RDC/SDIN = 1 INVSCLK = INVSYNC = 0
D17 D16 D2 D1 D0X
123 161718
BUSY
SYNC
SCLK
DOUT
CS, RD
CNVST
t
3
t
1
t
17
t
14
t
15
t
19
t
20
t
21
t
16
t
22
t
23
t
24
t
27
t
26
t
25
t
18
EXT/INT = 0
03084-0-040
Figure 34. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
SLAVE SERIAL INTERFACE
External Clock
The AD7678 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/
INT
pin is
held high. In this mode, several methods can be used to read
the data. The external serial clock is gated by
CS
. When
CS
and
RD
are both low, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive. Figure 35 and Figure 36 show the detailed timing
diagrams of these methods.
While the AD7678 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7678 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is recom-
mended that when an external clock is being provided, it is a
discontinuous clock that only toggles when BUSY is low or,
more importantly, that it does not transition during the latter
half of BUSY high.
External Discontinuous Clock Data Read after
Conversion
This mode is the most recommended of the serial slave modes.
Figure 35 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
low, the result of this conversion can be read while both
CS
and
RD
are low. Data is shifted out MSB first with 18 clock pulses,
and is valid on both the rising and falling edge of the clock.
Among the advantages of this method, the conversion perfor-
mance is not degraded because there are no voltage transients
on the digital interface during the conversion process. Also,
data can be read at speeds up to 40 MHz, accommodating both
slow digital host interface and the fastest serial reading.
Finally, in this mode only, the AD7678 provides a daisy-chain
feature using the RDC/SDIN input pin to cascade multiple
converters together. This feature is useful for reducing
component count and wiring connections when desired (for
instance, in isolated multiconverter applications).
An example of the concatenation of two devices is shown in
Figure 37. Simultaneous sampling is possible by using a
common
CNVST
signal. It should be noted that the RDC/SDIN
input is latched on the edge of SCLK opposite the one used to
shift out data on SDOUT. Thus, the MSB of the upstream
converter follows the LSB of the downstream converter on the
next SCLK cycle.
