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AD7678ASTZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
AD7678
Rev. A | Page 3 of 28
SPECIFICATIONS
Table 2. –40°C to +85°C, V
REF
= 4.096 V, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Parameter Conditions Min Typ Max Unit
RESOLUTION 18 Bits
ANALOG INPUT
Voltage Range V
IN+
– V
IN–
–V
REF
+V
REF
V
Operating Input Voltage V
IN+
, V
IN–
to AGND –0.1 AVDD + 0.1 V
Analog Input CMRR f
IN
= 100 kHz 65 dB
Input Current 100 kSPS Throughput 4 μA
Input Impedance
1
THROUGHPUT SPEED
Complete Cycle 10 μs
Throughput Rate 0 100 kSPS
DC ACCURACY
Integral Linearity Error –2.5 +2.5 LSB
2
Differential Linearity Error –1 +1.75 LSB
No Missing Codes 18 Bits
Transition Noise V
REF
= 5 V 0.7 LSB
Zero Error, T
MIN
to T
MAX
–40 ±40 LSB
Zero Error Temperature Drift ±0.5 ppm/°C
Gain Error, T
MIN
to T
MAX
3
–0.048 See Note 3 +0.048 % of FSR
Gain Error Temperature Drift ±1.6 ppm/°C
Power Supply Sensitivity AVDD = 5 V ± 5% ±4 LSB
AC ACCURACY
Signal-to-Noise f
IN
= 2 kHz, V
REF
= 5 V 101 dB
4
V
REF
= 4.096 V 98 100 dB
f
IN
= 10 kHz, V
REF
= 4.096 V 99.5 dB
f
IN
= 45 kHz, V
REF
= 4.096 V 98 dB
Dynamic Range V
IN+
= V
IN–
= V
REF
/2 = 2.5 V 103 dB
Spurious-Free Dynamic Range f
IN
= 2 kHz 120 dB
f
IN
= 10 kHz 117 dB
f
IN
= 45 kHz 110 dB
Total Harmonic Distortion f
IN
= 2 kHz –118 dB
f
IN
= 10 kHz –115 dB
f
IN
= 45 kHz –110 dB
Signal-to-(Noise + Distortion) f
IN
= 2 kHz 100 dB
f
IN
= 2 kHz, –60 dB Input 41 dB
–3 dB Input Bandwidth 900 kHz
SAMPLING DYNAMICS
Aperture Delay 2 ns
Aperture Jitter 5 ps rms
Transient Response Full-Scale Step 8.5 μs
Overvoltage Recovery 8.5 μs
REFERENCE
External Reference Voltage Range REF 3 4.096 AVDD + 0.1 V
REF Voltage with Reference Buffer REFBUFIN = 2.5 V 4.05 4.096 4.15 V
Reference Buffer Input Voltage Range REFBUFIN 1.8 2.5 2.6 V
REFBUFIN Input Current –1 +1 μA
REF Current Drain 100 kSPS Throughput 42 μA
AD7678
Rev. A | Page 4 of 28
Parameter Conditions Min Typ Max Unit
DIGITAL INPUTS
Logic Levels
V
IL
–0.3 +0.8 V
V
IH
2.0 DVDD + 0.3 V
I
IL
–1 +1 μA
I
IH
–1 +1 μA
DIGITAL OUTPUTS
Data Format
5
Pipeline Delay
6
V
OL
I
SINK
= 1.6 mA 0.4 V
V
OH
I
SOURCE
= –500 μA OVDD – 0.6 V
POWER SUPPLIES
Specified Performance
AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 DVDD + 0.3
7
V
Operating Current 100 kSPS Throughput
AVDD PDBUF High 2.6 mA
DVDD
8
1 mA
OVDD
8
40 μA
PDBUF High @ 100 kSPS 18 26 mW
PDBUF High @ 1 kSPS 180 μW
PDBUF Low @ 100 kSPS 31 mW
TEMPERATURE RANGE
9
Specified Performance T
MIN
to T
MAX
–40 +85 °C
1
See the Analog Inputs section.
2
LSB means Least Significant Bit. With the ±4.096 V input range, 1 LSB is 31.25 μV.
3
See the Definition of Specifications section. The nominal gain error is not centered at zero and is −0.029% of FSR. This specification is the deviation from this nominal
value. These specifications do not include the error contribution from the external reference, but do include the error contribution from the reference buffer if used.
4
All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
5
Data format parallel or serial 18-bit.
6
Conversion results are available immediately after completed conversion.
7
The maximum should be the minimum of 5.25 V and DVDD + 0.3 V.
8
Tested in Parallel Reading mode.
9
Contact factory for extended temperature range.
AD7678
Rev. A | Page 5 of 28
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Parameter Symbol Min Typ Max Unit
Refer to Figure 27 and Figure 28
Convert Pulse Width t
1
10 ns
Time between Conversions t
2
10 μs
CNVST LOW to BUSY HIGH Delay
t
3
35 ns
BUSY HIGH All Modes Except Master Serial Read after Convert t
4
1.5 μs
Aperture Delay t
5
2 ns
End of Conversion to BUSY LOW Delay t
6
10 ns
Conversion Time t
7
1.5 μs
Acquisition Time t
8
8.5 μs
RESET Pulsewidth t
9
10 ns
Refer to Figure 29, Figure 30, and Figure 31 (Parallel Interface Modes)
CNVST LOW to Data Valid Delay
t
10
1.5 μs
Data Valid to BUSY LOW Delay t
11
20 ns
Bus Access Request to Data Valid t
12
45 ns
Bus Relinquish Time t
13
5 15 ns
Refer to Figure 33 and Figure 34 (Master Serial Interface Modes)
1
CS LOW to SYNC Valid Delay
t
14
10 ns
CS LOW to Internal SCLK Valid Delay
t
15
10 ns
CS LOW to SDOUT Delay
t
16
10 ns
CNVST LOW to SYNC Delay
t
17
525 ns
SYNC Asserted to SCLK First Edge Delay
2
t
18
3 ns
Internal SCLK Period
2
t
19
25 40 ns
Internal SCLK HIGH
2
t
20
12 ns
Internal SCLK LOW
2
t
21
7 ns
SDOUT Valid Setup Time
2
t
22
4 ns
SDOUT Valid Hold Time
2
t
23
2 ns
SCLK Last Edge to SYNC Delay
2
t
24
3 ns
CS HIGH to SYNC HI-Z
t
25
10 ns
CS HIGH to Internal SCLK HI-Z
t
26
10 ns
CS HIGH to SDOUT HI-Z
t
27
10 ns
BUSY HIGH in Master Serial Read after Convert
2
t
28
See Table 4
CNVST LOW to SYNC Asserted Delay
t
29
1.5 μs
SYNC Deasserted to BUSY LOW Delay t
30
25 ns
Refer to Figure 35 and Figure 36 (Slave Serial Interface Modes)
External SCLK Setup Time t
31
5 ns
External SCLK Active Edge to SDOUT Delay t
32
3 18 ns
SDIN Setup Time t
33
5 ns
SDIN Hold Time t
34
5 ns
External SCLK Period t
35
25 ns
External SCLK HIGH t
36
10 ns
External SCLK LOW t
37
10 ns
1
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
2
In Serial Master Read during Convert mode. See Table 4 for Serial Master Read after Convert mode.
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AD7678ASTZ

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Analog to Digital Converters - ADC IC 18-Bit 100 kSPS
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