Data Sheet ADuCM320
Rev. C | Page 15 of 30
TIMING SPECIFICATIONS
I
2
C Timing
Table 3. I
2
C Timing in Standard Mode (100 kHz)
Slave
Parameter Description Min Typ Max Unit
t
L
SCL low pulse width 4.7 µs
t
H
SCL high pulse width 4.0 ns
t
SHD
Start condition hold time 4.0 µs
t
DSU
Data setup time 250 ns
t
DHD
Data hold time (SDA held internally for 300 ns after falling edge of SCL) 0 3.45 µs
t
RSU
Setup time for repeated start 4.7 µs
t
PSU
Stop condition setup time 4.0 µs
t
BUF
Bus-free time between a stop condition and a start condition 4.7 µs
t
R
Rise time for both SLC and SDA 1 µs
t
F
Fall time for both SLC and SDA 15 300 ns
t
VD;DAT
Data valid time 3.45 µs
t
VD;ACK
Data valid acknowledge time 3.45 µs
Table 4. I
2
C Timing in Fast Mode (400 kHz)
Slave
Parameter Description Min Typ Max Unit
t
L
SCL low pulse width 1.3 µs
t
H
SCL high pulse width 0.6 ns
t
SHD
Start condition hold time 0.3 µs
t
DSU
Data setup time 100 ns
t
DHD
Data hold time (SDA held internally for 300 ns after falling edge of SCL) 0 µs
t
RSU
Setup time for repeated start 0.6 µs
t
PSU
Stop condition setup time 0.3 µs
t
BUF
Bus-free time between a stop condition and a start condition 1.3 µs
t
R
Rise time for both SCL and SDA 20 300 ns
t
F
Fall time for both SCL and SDA 15 300 ns
t
VD;DAT
Data valid time
0.9
µs
t
VD;ACK
Data valid acknowledge time 0.9 µs
Figure 2. I
2
C Compatible Interface Timing
12272-002
SDA (I/O)
MSB
LSB ACK MSB
1982–71
SCL (I)
P S
START
CONDITION
REPEATED
START
STOP
CONDITION
S(R)
t
DSU
t
H
t
L
t
SHD
t
PSU
t
DSU
t
BUF
t
DHD
t
VD; DAT
t
VD; ACK
t
R
t
F
t
F
t
R
t
DHD
t
RSU
ADuCM320 Data Sheet
Rev. C | Page 16 of 30
SPI Timing
Table 5. SPI Master Mode Timing (Phase Mode = 1)
Parameter Description Min Typ Max Unit
t
SL
SCLK low pulse width (SPIDIV + 1) × t
HCLK
/2 ns
t
SH
SCLK high pulse width (SPIDIV + 1) × t
HCLK
/2 ns
t
DAV
Data output valid after SCLK edge 0 3 ns
t
DSU
Data input setup time before SCLK edge ½ SCLK ns
t
DHD
Data input hold time after SCLK edge SCLK ns
t
DF
Data output fall time SCLK ns
t
DR
Data output rise time 25 ns
t
SR
SCLK rise time
25
ns
t
SF
SCLK fall time 20 ns
Figure 3. SPI Master Mode Timing (Phase Mode = 1)
12727-003
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
MOSI MSB BITS 6 TO 1 LSB
MISO MSB IN BITS 6 TO 1 LSB IN
t
SH
t
SL
t
SR
t
SF
t
DR
t
DF
t
DAV
t
DSU
t
DHD
Data Sheet ADuCM320
Rev. C | Page 17 of 30
Table 6. SPI Master Mode Timing (Phase Mode = 0)
Parameter Description Min Typ Max Unit
t
SL
SCLK low pulse width (SPIDIV + 1) × t
HCLK
/2 ns
t
SH
SCLK high pulse width (SPIDIV + 1) × t
HCLK
/2 ns
t
DAV
Data output valid after SCLK edge 0 3 ns
t
DOSU
Data output setup before SCLK edge ½ SCLK ns
t
DSU
Data input setup time before SCLK edge SCLK ns
t
DHD
Data input hold time after SCLK edge SCLK ns
t
DF
Data output fall time 25 ns
t
DR
Data output rise time 25 ns
t
SR
SCLK rise time 20 ns
t
SF
SCLK fall time 20 ns
Figure 4. SPI Master Mode Timing (Phase Mode = 0)
12272-004
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
t
SH
t
SL
t
SR
t
SF
MOSI MSB BITS 6 TO 1 LSB
MISO MSB IN BITS 6 TO 1 LSB IN
t
DR
t
DF
t
DAV
t
DOSU
t
DSU
t
DHD

ADUCM320BBCZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
ARM Microcontrollers - MCU 80Mhz Cortex M3 wi 14Bit Analog for CFP
Lifecycle:
New from this manufacturer.
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