Data Sheet ADuCM320
Rev. C | Page 21 of 30
ABSOLUTE MAXIMUM RATINGS
All requirements applicable to each pin must be met. Where
multiple limits apply to a pin each one must be met individually.
The limits apply according to the functionality of the pins at the
time. Pins that can be either analog or digital, that is, that have
two types indicated in the pin descriptions, must meet the limits
for both types. For pin types, see Table 11.
When powered up, it is required that all ground pins plus
ADC_REFN be connected together to a node referred to as
GND in Table 10. The limits that are listed must be reduced by
any difference between any GNDs. Also, it is required that
AVDD3 is connected to AVDD4 and that IOVDD1 to IOVDD3
are connected together.
Table 10. Absolute Maximum Ratings
Parameter Rating
Any Pin to GND 0.3 V to +3.9 V
Any PVDDx Pin to GND −0.3 V to +2.8 V
MDIO
1
, MCK, and PRTADDR0-4 in
MDIO Mode to GND
0.3 V to +2.1 V
Between Any of AVDDx, IOVDDx, and
VDD1 Pins
0.3 V to +0.3 V
Any Type I Pin to GND
2
0.3 V to IOVDDx + 0.3 V
Any Type AI or AO Pin to GND
3
0.3 V to AVDDx + 0.3 V
Any IDACx, CDAMPx, IDACTST, IREF
to GND
0.3 V to PVDDx + 0.3 V
ADC_REFP to GND 0.3 V to AVDDx + 0.3 V
Total Positive GPIO Pin Currents 0 mA to 30 mA
Total Negative GPIO Pin Currents 30 mA to 0 mA
Maximum Power Dissipation 1 W
Operating Ambient Temperature
Range
40°C to +105°C
Storage Temperature Range 65°C to +160°C
Operating Junction Temperature
Range
40°C to +120°C
ESD HBM 2 kV
ESD FICDM 1 kV
1
Note this pin is always in MDIO mode.
2
This limit does not apply if no current can be drawn by external circuits on
IOVDDx because then IOVDD follows to a suitable level.
3
This limit does not apply if no current can be drawn by external circuits on
AVDDx because then AVDD follows to a suitable level.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
ADuCM320 Data Sheet
Rev. C | Page 22 of 30
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 8. Pin Configuration
Table 11. Pin Function Descriptions
Pin
No. Mnemonic Type
1
Description
B2
RESET
I Reset Input (Active Low). An internal pull-up resistor is included.
C2 P0.0/SCLK0/PLAI[0] I/O Digital I/O Port 0.0 (P0.0).
SPI0 Clock (SCLK0).
Input to PLA Element 0 (PLAI[0]).
D2 P0.1/MISO0/PLAI[1] I/O Digital I/O Port 0.1 (P0.1).
SPI0 Master In, Slave Out (MISO0).
Input to PLA Element 1 (PLAI[1]).
D1 P0.2/MOSI0/PLAI[2] I/O Digital I/O Port 0.2 (P0.2).
SPI0 Master Out, Slave In (MOSI0).
Input to PLA Element 2 (PLAI[2]).
E3 P0.3/IRQ0/CS0/PLACLK0/PLAI[3] I/O Digital I/O Port 0.3 (P0.3).
External Interrupt 0 (IRQ0).
SPI0 Chip Select 0 (CS0). When using SPI0, configure this pin as CS0.
PLA Clock 0 (PLACLK0).
Input to PLA Element 3 (PLAI[3]).
E2 P0.4/SCL0/PLAO[2] I/O Digital I/O Port 0.4 (P0.4).
I
2
C0 Serial Clock (SCL0).
Output of PLA Element 2 (PLAO[2]).
E1 P0.5/SDA0/PLAO[3] I/O Digital I/O Port 0.5 (P0.5).
I
2
C0 Serial Data (SDA0).
Output of PLA Element 3 (PLAO[3]).
1
A
B
C
D
E
F
G
H
J
K
L
2
3
4 5
6
7
8 9
10
11
IDAC_
TST
IDAC0
IDAC2
IOVDD1
IOGND1
P3.3/
PR
TADDR3/
PLAI[15]
P0.0/
SCLK0/
PLAI[0]
CDAMP0
CDAMP2 CDAMP3
CDAMP1
IDAC1
IREF
IDAC3PGND
DGND2
SWCLK
AIN15/
P4.7
AIN14/
P4.6
AIN12/
P4.4
AIN1
1/
BUF_
VREF2V5
AIN10
AIN7
AIN2
AIN1
AIN0
AGND1
VDAC4
VDAC7/
P5.2
VDAC6/
P5.1
XTALI
IOVDD3
IOGND3
VDAC3/
P5.0
VDAC1
VDD1
AVDD3
AGND2
AGND3
AIN3
AIN4
AIN6
AIN5
AIN9/
P4.3
AIN8/
P4.2
VDAC0/
P5.3
VDAC2/
P3.7/
PLAO[29]
VDAC5
DGND1
AGND4
AIN13/
P4.5
AVDD4
SWDIO
IOGND2
IOVDD2
PGND
PVDD0
PVDD2
PVDD3
PVDD1
RESET
12272-008
P1.0/SIN/
ECLKIN/
PLAI[4]
P1.2/
PWM0/
PLAI[6]
P1.1/SOUT/
PLACLK1/
PLAI[5]
P2.4/IRQ5/
ADCCONV/
PWM6/
PLAO[18]
P1.3/
PWM1/
PLAI[7]
P1.4/
PWM2/
SCLK1/
PLAO[10]
P1.5/
PWM3/
MISO1/
PLAO[
11]
P1.6/
PWM4/
MOSI1/
PLAO[12]
P1.7/IRQ1/
PWM5/
CS1/
PLAO[13]
P2.0/IRQ2/
PWMTRIP/
PLACLK2/
PLAI[8]
P2.2/
IRQ4/POR/
CLKOUT/
PLAI[10]
P2.3/BM
P0.2/
MOSI0/
PLAI[2]
P0.5/
SDA0/
PLAO[3]
P2.6/
IRQ7/
PLAO[20]
P0.7/
SDA1/
PLAO[5]
P0.6/
SCL1/
PLAO[4]
P3.0/
PR
TADDR0/
PLAI[12]
P3.1/
PRTADDR1/
PLAI[13]
P2.7/
IRQ8/
PLAO[21]
P3.5/
MCK/
PLAO[27]
XT
ALO
MDIO
P0.4/
SCL0/
PLAO[2]
P0.3/
IRQ0/CS0/
PLACLK0/
PLAI[3]
P0.1/
MISO0/
PLAI[1]
P3.2/
PRT
ADDR2/
PLAI[14]
P3.4/
PRT
ADDR4/
PLAO[26]
A
VDD_
REG0
AVDD_
REG1
VREF_1V2
ADC_
REF
P
ADC_
REFN
DVDD_
2V5
DVDD_1V8
ADuCM320
TOP VIEW
(Not to Scale)
Data Sheet ADuCM320
Rev. C | Page 23 of 30
Pin
No. Mnemonic Type
1
Description
F3 P0.6/SCL1/PLAO[4] I/O Digital I/O Port 0.6 (P0.6).
I
2
C1 Serial Clock (SCL1).
Output of PLA Element 4 (PLAO[4]).
F2 P0.7/SDA1/PLAO[5] I/O Digital I/O Port 0.7 (P0.7).
I
2
C1 Serial Data (SDA1).
Output of PLA Element 5 (PLAO[5]).
B9 P1.0/SIN/ECLKIN/PLAI[4] I/O Digital I/O Port 1.0 (P1.0).
UART Input (SIN).
External Input Clock (ECLKIN).
Input to PLA Element 4 (PLAI[4]).
B10 P1.1/SOUT/PLACLK1/PLAI[5] I/O Digital I/O Port 1.1 (P1.1).
UART Output (SOUT)
PLA Clock 1(PLACLK1).
Input to PLA Element 5 (PLAI[5]).
B11 P1.2/PWM0/PLAI[6] I/O Digital I/O Port 1.2 (P1.2).
PWM Output 0 (PWM0).
Input to PLA Element 6 (PLAI[6]).
C6 P1.3/PWM1/PLAI[7] I/O Digital I/O Port 1.3 (P1.3).
PWM Output 1 (PWM1).
Input to PLA Element 7 (PLAI[7]).
C7 P1.4/PWM2/SCLK1/PLAO[10] I/O Digital I/O Port 1.4 (P1.4).
PWM Output 2 (PWM2).
SPI1 Clock (SCLK1).
Output of PLA Element 10 (PLAO[10]).
C8 P1.5/PWM3/MISO1/PLAO[11] I/O Digital I/O Port 1.5 (P1.5).
PWM Output 3 (PWM3).
SPI1 Master In, Slave Out (MISO1).
Output of PLA Element 11 (PLAO[11]).
C9 P1.6/PWM4/MOSI1/PLAO[12] I/O Digital I/O Port 1.6 (P1.6).
PWM Output 4 (PWM4).
SPI1 Master Out, Slave Input (MOSI1).
Output of PLA Element 12 (PLAO[12]).
C10 P1.7/IRQ1/PWM5/CS1/PLAO[13] I/O Digital I/O Port 1.7 (P1.7).
External Interrupt 1 (IRQ1).
PWM Output 5 (PWM5).
SPI1 Chip Select 1 (CS1). When using SPI1, configure this pin as CS1.
Output of PLA Element 13 (PLAO[13]).
C5 P2.0/IRQ2/PWMTRIP/PLACLK2/PLAI[8] I/O Digital I/O Port 2.0 (P2.0).
External Interrupt 2 (IRQ2).
PWM Trip (PWMTRIP).
PLA Input Clock 2 (PLACLK2).
Input to PLA Element 8 (PLAI[8]).
C4 P2.2/IRQ4/
POR
/CLKOUT/PLAI[10] I/O Digital I/O Port 2.2 (P2.2).
External Interrupt 4 (IRQ4).
Reset Output (
POR
). This pin function is an output and it is the default for Pin C4.
Clock Output (CLKOUT).
Input to PLA Element 10 (PLAI[10]).
C3
P2.3/BM
I/O
Digital I/O Port 2.3 (P2.3).
Boot Mode (BM). This pin determines the start-up sequence after every reset.
Pull-up is enabled at power-up.

ADUCM320BBCZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
ARM Microcontrollers - MCU 80Mhz Cortex M3 wi 14Bit Analog for CFP
Lifecycle:
New from this manufacturer.
Delivery:
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