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ADUCM320BBCZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
ADuCM320 Data Sheet
Rev. C | Page 24 of 30
Pin
No. Mnemonic Type
1
Description
D9 P2.4/IRQ5/ADCCONV/PWM6/PLAO[18] I/O Digital I/O Port 2.4 (P2.4).
External Interrupt 5 (IRQ5).
External Input to Start ADC Conversions (ADCCONV).
PWM Output 6 (PWM6).
Output of PLA Element 18 (PLAO[18]).
F1 P2.6/IRQ7/PLAO[20] I/O Digital I/O Port 2.6 (P2.6).
External Interrupt 7 (IRQ7).
Output of PLA Element 20 (PLAO[20]).
G1
P2.7/IRQ8/PLAO[21]
I/O
Digital I/O Port 2.7 (P2.7).
External Interrupt 8 (IRQ8).
Output of PLA Element 21 (PLAO[21]).
G3 P3.0/PRTADDR0/PLAI[12] I/O Digital I/O Port 3.0 (P3.0).
MDIO Port Address Bit 0 (PRTADDR0). See the digital inputs parameter in Table 1
for details.
Input to PLA Element 12 (PLAI[12]).
G2 P3.1/PRTADDR1/PLAI[13] I/O Digital I/O Port 3.1 (P3.1).
MDIO Port Address Bit 1 (PRTADDR1). See the digital inputs parameter in Table 1
for details.
Input to PLA Element 13 (PLAI[13]).
D3
P3.2/PRTADDR2/PLAI[14]
I/O
Digital I/O Port 3.2 (P3.2).
MDIO Port Address Bit 2 (PRTADDR2). See the digital inputs parameter in Table 1
for details.
Input to PLA Element 14 (PLAI[14]).
B3 P3.3/PRTADDR3/PLAI[15] I/O Digital I/O Port 3.3 (P3.3).
MDIO Port Address Bit 3 (PRTADDR3). See the digital inputs parameter in Table 1
for details.
Output of PLA Element 15 (PLAI[15]).
C11 P3.4/PRTADDR4/PLAO[26] I/O Digital I/O Port 3.4 (P3.4).
MDIO Port Address Bit 4 (PRTADDR4). See the digital inputs parameter in Table 1
for details.
Output of PLA Element 26 (PLAO[26]).
H1 P3.5/MCK/PLAO[27] I/O Digital I/O Port 3.5 (P3.5).
MDIO Clock (MCK) See the digital inputs parameter in Table 1 for more details.
Output of PLA Element 27 (PLAO[27]).
H3 MDIO I/O MDIO Data.
E9 SWCLK I Serial Wire Debug Clock.
E10 SWDIO I/O Serial Wire Bidirectional Data.
F11 VREF_1V2 S 1.2 V Reference. This pin cannot be used to source current externally. Connect
VREF_1V2 to AGNDx via a 470 nF capacitor.
A11 IREF AI IDAC Reference Current. This pin generates the reference current for the IDACs
and is set by an external resistor, R
EXT
. Connect R
EXT
from IREF to AGND4.
J6 AIN0 AI Analog Input 0.
J7 AIN1 AI Analog Input 1.
J8 AIN2 AI Analog Input 2.
K8 AIN3 AI Analog Input 3.
L8 AIN4 AI Analog Input 4.
L9 AIN5 AI Analog Input 5. AIN5 can be the −ve input for the comparator.
K9
AIN6
AI
Analog Input 6. AIN6 is also the +ve input for the comparator.
J9 AIN7 AI Analog Input 7.
L10 AIN8/P4.2 AI/I/O Analog Input 8 (AIN8).
Digital I/O Port 4.2 (P4.2).
K10 AIN9/P4.3 AI/I/O Analog Input 9 (AIN9).
Digital I/O Port 4.3 (P4.3).
J10 AIN10 AI Analog Input 10.
Data Sheet ADuCM320
Rev. C | Page 25 of 30
Pin
No. Mnemonic Type
1
Description
J11 AIN11/BUF_VREF2V5 AI/AO Analog Input 11 (AIN11).
Buffered 2.5 V Bias (BUF_VREF2V5). The maximum load = 1.2 mA. Connect
BUF_VREF2V5 to AGNDx via a 100 nF capacitor.
H10 AIN12/P4.4 AI/I/O Analog Input 12 (AIN12).
Digital I/O Port 4.4 (P4.4).
G10 AIN13/P4.5 AI/I/O Analog Input 13 (AIN13).
Digital I/O Port 4.5 (P4.5).
H9
AIN14/P4.6
AI/I/O
Analog Input 14 (AIN14).
Digital I/O Port 4.6 (P4.6).
G9 AIN15/P4.7 AI/I/O Analog Input 15 (AIN15).
Digital I/O Port 4.7 (P4.7).
L5 VDAC0/P5.3 AO/I/O Voltage DAC0 Output (VDAC0).
Digital I/O Port 5.3 (P5.3).
K5 VDAC1 AO Voltage DAC1 Output.
L4 VDAC2/P3.7/PLAO[29] AO/I/O Voltage DAC2 Output (VDAC2).
Digital I/O Port 3.7 (P3.7).
Output of PLA Element 29 (PLAO[29]).
K4 VDAC3/P5.0 AO/I/O Voltage DAC3 Output (VDAC3).
Digital I/O Port 5.0 (P5.0).
J4
VDAC4
AO
Voltage DAC4 Output (VDAC4).
L3 VDAC5 AO Voltage DAC5 Output (VDAC5).
K3 VDAC6/P5.1 AO/I/O Voltage DAC6 Output (VDAC6).
Digital I/O Port 5.1 (P5.1).
J3 VDAC7/P5.2 AO/I/O Voltage DAC7 Output (VDAC7).
Digital I/O Port 5.2 (P5.2).
A2 IDAC0 AO IDAC0. 0 mA to 150 mA full-scale output.
A3 PVDD0 S Power for IDAC0.
B4 CDAMP0 AI Damping Capacitor 0. Connect damping capacitor from this pin to PVDD0.
A10 IDAC1 AO IDAC1. 0 mA to 150 mA full-scale output.
A9 PVDD1 S Power for IDAC1.
B8 CDAMP1 AI Damping Capacitor 1. Connect damping capacitor from this pin to PVDD1.
A5 IDAC2 AO IDAC2. 0 mA to 150 mA full-scale output.
A4 PVDD2 S Power for IDAC2.
B5 CDAMP2 AI Damping Capacitor 2. Connect damping capacitor from this pin to PVDD2.
A7 IDAC3 AO IDA3C. 0 mA to 150 mA full-scale output.
A8 PVDD3 S Power for IDAC3.
B7
CDAMP3
AI
Damping Capacitor 3. Connect damping capacitor from this pin to PVDD3.
B6 PGND S Power Supply Ground for IDACs.
A6 PGND S Power Supply Ground for IDACs.
A1 IDAC_TST AI/AO Pin for IDAC Test Purposes. Leave IDAC_TST unconnected.
L2 DVDD_1V8 AO 1.8 V Digital Supply. A 470 nF capacitor to DGND1 must be connected to this pin
to stabilize the internal 1.8 V regulator that supplies flash memory and the ARM
Cortex-M3 processor.
K2 DVDD_2V5 AO 2.5 V Digital Supply. A 470 nF capacitor to IOGND3 must be connected to this
pin to stabilize the internal 2.5 V regulator that supplies the analog digital
control.
F9 AVDD_REG0 AO Analog Regulator 0 Supply. A 470 nF capacitor to AGND4 must be connected to
this pin to stabilize the internal 2.5 V regulator that supplies the ADC.
F10 AVDD_REG1 AO Analog Regulator 1 Supply. Output of 2.5 V on-chip LDO regulator. A 470 nF
capacitor to AGND4 must be connected to this pin. This regulator supplies the
IDACs.
L1 DGND1 S Digital Ground 1 for DVDD_1V8.
D10 DGND2 S Digital Ground 2. Connect to DGND1.
B1 IOVDD1 S 3.3 V GPIO Supply.
ADuCM320 Data Sheet
Rev. C | Page 26 of 30
Pin
No. Mnemonic Type
1
Description
D11 IOVDD2 S 3.3 V GPIO Supply and Interdie Communications.
J1 IOVDD3 S 3.3 V GPIO Supply.
C1 IOGND1 S Ground for IOVDD1.
E11 IOGND2 S Ground for IOVDD2.
K1 IOGND3 S Ground for IOVDD3 and Interdie Communications.
J5 AGND1 S Analog Ground for VDD1.
K7 AGND2 S ESD Ground for Pad Ring.
L7 AGND3 S Ground for AVDD3.
H11
AGND4
S
Ground for AVDD4, AVDD_REG0, and AVDD_REG1.
K6 VDD1 S 3.3 V Supply for Digital Die.
L6 AVDD3 S VDAC and IDAC Supply (3.3 V).
G11 AVDD4 S ADC Supply (3.3 V).
L11 ADC_REFN AO/A Decoupling Capacitor Connection for ADC Reference Buffer. Connect this pin to
AGND4.
K11 ADC_REFP AO/A Decoupling Capacitor Connection for ADC Reference Buffer. Connect this pin to
a 4.7 µF capacitor to the ADC_REFN pin. ADC_REFP can be overdriven by an
external reference.
H2 XTALO O Output from the Crystal Oscillator Inverter. When not using an external crystal,
leave XTALO unconnected.
J2
XTALI
I
Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator
Circuits. When not using an external crystal, connect XTALI to DGND.
1
AI is analog input, AO is analog output, I is digital input, O is digital output, S is supply.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

ADUCM320BBCZ

Mfr. #:
Buy ADUCM320BBCZ
Manufacturer:
Analog Devices Inc.
Description:
ARM Microcontrollers - MCU 80Mhz Cortex M3 wi 14Bit Analog for CFP
Lifecycle:
New from this manufacturer.
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