HIP2120, HIP2121
13
FN7668.0
December 23, 2011
Power Dissipation
The dissipation of the HIP2120/21 is dominated by the gate
charge required by the driven bridge FETs and the switching
frequency. The internal bias and boot diode also contribute to the
total dissipation but these losses are usually insignificant
compared to the gate charge losses.
The calculation of the power dissipation of the HIP2120/21 is
very simple.
GATE POWER (FOR THE HO AND LO OUTPUTS)
P
gate
= 4 x Q
gate
x Freq x VDD
where
Q
gate
is the charge of the driven bridge FET at VDD, and
Freq is the switching frequency.
BOOT DIODE DISSIPATION
I
diode_avg
= Q
gate
x Freq
P
diode
= I
diode_avg
x 0.6V
where 0.6V is the diode conduction voltage
BIAS CURRENT
P
bias
= I
bias
x VDD
where I
bias
is the internal bias current of the HIP2120/21 at the
switching frequency
TOTAL POWER DISSIPATION
P
total
= P
gate
+ P
diode
+ P
bias
OPERATING TEMPERATURES
T
j
= P
total
x
JA
+ T
amb
where T
j
is the junction temperature at the operating air
temperature, T
amb
, in the vicinity of the part.
T
j
= P
total
x
JC
+ T
PCB
where T
j
is the junction temperature with the operating
temperature of the PCB, T
PCB
, measured where the EPAD is
soldered.
PC Board Layout
The AC performance of the HIP2120/21 depends significantly on
the design of the PC board. The following layout design
guidelines are recommended to achieve optimum performance
from the HIP2120/21:
• Understand well how power currents flow. The high amplitude
di/dt currents of the bridge FETs will induce significant voltage
transients on the associated traces.
• Keep power loops as short as possible by paralleling the
source and return traces.
• Use planes where practical; they’re usually more effective than
parallel traces.
• Planes can also be non-grounded nodes.
• Avoid paralleling high di/dt traces with low level signal lines.
High di/dt will induce currents in the low level signal lines.
• When practical, minimize impedances in low level signal
circuits; the noise, magnetically induced on a 10k resistor, is
10x larger than the noise on a 1k resistor.
• Be aware of magnetic fields emanating from transformers and
inductors. Core gaps in these structures are especially bad for
emitting flux.
• If you must have traces close to magnetic devices, align the
traces so that they are parallel to the flux lines.
• The use of low inductance components such as chip resistors
and chip capacitors is recommended.
• Use decoupling capacitors to reduce the influence of parasitic
inductors. To be effective, these capacitors must also have the
shortest possible lead lengths. If vias are used, connect several
paralleled vias to reduce the inductance of the vias.
• It may be necessary to add resistance to dampen resonating
parasitic circuits. The most likely circuit will be the HO and LO
outputs. In PCB designs with long leads on the LI and HI inputs,
it may also be necessary to add series resistors with the LI and
HI inputs.
• Keep high dv/dt nodes away from low level circuits. Guard
banding can be used to shunt away dv/dt injected currents
from sensitive circuits. This is especially true for the PWM
control circuits.
• Avoid having a signal ground plane under a high dv/dt circuit.
This will inject high di/dt currents into the signal ground paths.
• Do power dissipation and voltage drop calculations of the
power traces. Most PCB/CAD programs have built in tools for
calculation of trace resistance.
• Large power components (Power FETs, Electrolytic capacitors,
power resistors, etc.) will have internal parasitic inductance,
which cannot be eliminated. This must be accounted for in the
PCB layout and circuit design.
• If you simulate your circuits, consider including parasitic
components.
