Semiconductor Components Industries, LLC, 2017
February, 2017 − Rev. 9
1 Publication Order Number:
B300/D
BelaSigna 300
Audio Processor for Portable
Communication Devices
Introduction
BelaSigna
300 is a DSP−based mixed−signal audio processing
system that delivers superior audio clarity without compromising size
or battery life. The processor is specifically designed for monaural
portable communication devices requiring high performance audio
processing capabilities and programming flexibility when form−factor
and power consumption are key design constraints.
The efficient dual−MAC 24−bit CFX DSP core, together with the
HEAR configurable accelerator signal processing engine, high speed
debugging interface, advanced algorithm security system, state−of−
the−art analog front end, Class D output stage and much more,
constitute an entire system on a single chip, which enables
manufacturers to create a range of advanced and unique products. The
system features a high level of instructional parallelism, providing
highly efficient computing capability. It can simultaneously execute
multiple advanced adaptive noise reduction and echo cancellation
algorithms, and uses an asymmetric dual−core patented architecture to
allow for more processing in fewer clock cycles, resulting in reduced
power consumption.
BelaSigna 300 is supported by a comprehensive suite of
development tools, hands−on training, full technical support and a
network of solution partners offering software and engineering
services to help speed product design and shorten time to market.
Key Features
Flexible DSP−based System: a complete DSP−based, mixed−signal
audio system consisting of the CFX core, a fully programmable,
highly cycle−efficient, dual−Harvard architecture 24−bit DSP
utilizing explicit parallelism; the HEAR configurable accelerator for
optimized signal processing; and an efficient input/output controller
(IOC) along with a full complement of peripherals and interfaces,
which optimize the architecture for audio processing at extremely
low power consumption
Ultra−low−power: typically 1−5 mA
Excellent Audio Fidelity: up to 110 dB input dynamic range,
exceptionally low system noise and low group delay
Miniature Form Factor: available in a miniature 3.63 mm x
2.68 mm x 0.92 mm (including solder balls) WLCSP package.
Multiple Audio Input Sources: four input channels from five input
sources (depends on package selection) can be used simultaneously
for multiple microphones or direct analog audio inputs
Full Range of Configurable Interfaces: including a fast I
2
C−based
interface for download, debug and general communication, a highly
configurable PCM interface to stream data into and out of the device,
a high−speed UART, an SPI port and 5 GPIOs
www.onsemi.com
MARKING DIAGRAM
WLCSP−35
W SUFFIX
CASE 567AG
BELASIGNA300
35−02−G
XXXXYZZ
BELASIGNA300 = Device Code
35 = Number of Balls
02 = Revision of Die
G = Pb−Free
XXXX = Date Code
Y = Assembly Plant Identifier
= (May be Two Characters)
ZZ = Traceability Code
Device Package
ORDERING INFORMATION
B300W35A109XXG WLCSP
(Pb−Free)
Shipping
2500 / Tape &
Reel
For information on tape and reel specifications, in
-
cluding part orientation and tape sizes, please refe
r
to our Tape and Reel Packaging Specification
s
Brochure, BRD8011/D.
BelaSigna 300
www.onsemi.com
2
Integrated A/D Converters and Powered Output:
minimize need for external components
Flexible Clocking Architecture: supports speeds up to
40 MHz
“Smart” Power Management: including low current
standby mode requiring only 0.06 mA
Diverse Memory Architecture: 4864x48−bit words of
shared memory between the CFX core and the HEAR
accelerator plus 8−Kword DSP core data memory,
12−Kwords of 32−bit DSP core program memory as
well as other memory banks
Data Security: sensitive program data can be
encrypted for storage in external NVRAM to prevent
unauthorized parties from gaining access to proprietary
software intellectual property, 128−bit AES encryption
Development Tools: interface hardware with USB
support as well as a full IDE that can be used for every
step of program development including testing and
debugging
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
Contents
Introduction 1....................................................................................
Figures and Data 3.................................................................................
Mechanical Information and Circuit Design Guidelines 6..................................................
Architecture Overview 11...........................................................................
Application Diagrams 24...........................................................................
Assembly Information 25...........................................................................
Miscellaneous 26..................................................................................
BelaSigna 300
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3
Figures and Data
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter Min Max Unit
Voltage at any input pin −0.3 2.0 V
Operating supply voltage (Note 1) 0.9 2.0 V
Operating temperature range (Note 2) −40 85 °C
Storage temperature range (Note 3) −55 85 °C
Caution: Class 2 ESD Sensitivity, JESD22−A114−B (2000 V)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Functional operation only guaranteed below 0°C for digital core (VDDC) and system voltages above 1.0 V.
2. Parameters may exceed listed tolerances when out of the temperature range 0 to 50°C.
3. Extended range −55 to 125°C for storage temperature is under qualification.
Electrical Performance Specifications
The tests were performed at 20°C with a clean 1.8 V supply voltage. BelaSigna 300 was running in low voltage mode (VDDC = 1.2 V).
The system clock (SYS_CLK) was set to 5.12 MHz and the sampling frequency is 16 kHz unless otherwise noted.
Parameters marked as screened are tested on each chip. Other parameters are qualified but not tested on every part.
Table 2. ELECTRICAL SPECIFICATIONS
Description
Symbol Conditions Min Typ Max Units Screened
OVERALL
Supply voltage
V
BAT
The WLCSP package option
will not operate properly below
1.8 V if it relies on an external
EEPROM powered by VBAT.
0.9 1.8 2.0 V
Current consumption I
BAT
Filterbank, 100% CFX usage,
5.12 MHz, 16 kHz
Ambient room temperature
750
mA
WDRC, VBAT = 1.8 V
Excludes output drive current
Ambient room temperature
600
mA
AEC, VBAT = 1.8 V
Excludes output drive current
Ambient room temperature
2.1 mA
Theoretical maximum
Excludes output drive current
Ambient room temperature
10 mA
Deep Sleep current
Ambient room temperature,
VBAT = 1.25 V
26 40
mA
Deep Sleep current
Ambient room temperature,
VBAT = 1.8 V
62 160
mA
VREG (1 mF External Capacitor)
Regulated voltage output
V
REG
0.95 1.00 1.05 V
Regulator PSRR V
REG_PSRR
1 kHz 50 55 dB
Load current I
LOAD
2 mA
Load regulation LOAD
REG
6.1 6.5 mV/mA
Line regulation LINE
REG
2 5 mV/V
VDBL (1 mF External Capacitor)
Regulated doubled voltage
output
VDBL 1.9 2.0 2.1 V
Regulator PSRR VDBL
PSRR
1 kHz 35 41 dB
Load current I
LOAD
2.5 mA

B300D44A102XXG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Audio DSPs BELASIGNA 300
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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