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Table 7. NON−CRITICAL SIGNALS
Pin Name Description Routing Guideline
CAP0, CAP1 Internal charge pump − capacitor connection Place 100 nF capacitor close to pins
SDA, SCL I2C port Keep as short as possible
GPIO[3..0] General−purpose I/O Not critical
UART_RX, UART_TX General−purpose UART Not critical
PCM_FRAME, PCM_CLK, PCM_OUT,
PCM_IN
PCM port Keep away from analog input lines
LSAD[4..1] Low−speed A/D converters Not critical
SPI_CLK, SPI_CS, SPI_SERI, SPI_SERO Serial peripheral interface port
Connect to EEPROM
Keep away from analog input lines
Audio Inputs
The audio input traces should be as short as possible. The
input impedance of each audio input pad (e.g., AI0, AI1,
AI2, AI3, AI4) is high (approximately 500 kW); therefore a
10 nF capacitor is sufficient to decouple the DC bias. This
capacitor and the internal resistance form a first−order
analog high pass filter whose cutoff frequency can be
calculated by f
3dB
(Hz) = 1/(R x C x 2π), which results in
~30 Hz for a 10 nF capacitor. This 10 nF capacitor value
applies when the preamplifier is being used, in other words,
when a non−unity gain is applied to the signals. When the
preamplifier is by−passed, the impedance is reduced; hence,
the cut−off frequency of the resulting high−pass filter could
be too high. In such a case, the use of a 30−40 nF serial
capacitor is recommended. In cases where line−level analog
inputs without DC bias are used, the capacitor may be
omitted for transparent bass response.
BelaSigna 300 provides microphone power supply
(VREG) and ground (AGND). Keep audio input traces
strictly away from output traces. A 2.0 V microphone bias
might also be provided by the VDBL power supply.
Digital outputs (RCVR) MUST be kept away from
microphone inputs to avoid cross−coupling.
Audio Outputs
The audio output traces should be as short as possible. The
trace length of RCVR+ and RCVR− should be
approximately the same to provide matched impedances.
Recommendation for Unused Pins
The table below shows the recommendation for each pin
when they are not used.
Table 8. RECOMMENDATIONS FOR UNUSED PADS
WLCSP Ball Index BelaSigna 300 Signal Name Recommended Connection when Not Used
B2 RCVR_HP+ Do not connect
C3 RCVR+ Do not connect
A3 RCVR− Do not connect
B4 RCVR_HP− Do not connect
A11 AI4 Connect to AGND
N/A AI3/LOUT3 Connect to AGND
B12 AI2/LOUT2 Connect to AGND
A13 AI1/LOUT1 Connect to AGND
B14 AI0/LOUT0 Connect to AGND
D14 GPIO[4]/LSAD[4] Do not connect
E13 GPIO[3]/LSAD[3] Do not connect
C13 GPIO[2]/LSAD[2] Do not connect
D12 GPIO[1]/LSAD[1]/UART−RX Do not connect
E11 GPIO[0]/UART−TX Do not connect
E9 EXT_CLK Do not connect
E7 SPI_CLK Do not connect
C7 SPI_SERI Do not connect
BelaSigna 300
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Table 8. RECOMMENDATIONS FOR UNUSED PADS (continued)
WLCSP Ball Index Recommended Connection when Not UsedBelaSigna 300 Signal Name
D6 SPI_CS Do not connect
E5 SPI_SERO Do not connect
D4 PCM_FR Do not connect
E3 PCM_SERI Do not connect
D2 PCM_SERO Do not connect
C1 PCM_CLK Do not connect
E1 Reserved Connect to GND
Architecture Overview
The architecture of BelaSigna 300 is shown in Figure 2.
Figure 2. BelaSigna 300 Architecture: A Complete Audio Processing System
Watchdog
Timer
Timer 1
Power
Management
Power−On
Reset
Clock
Management
IP Protection
IOC (Input Side)
MUX
Timer 2
GPIO
UART
SPI
Output
Driver
Upsampling
CFX
24−bit DSP
Data Memory
Program Memory
Shared
Interface
(Input Side)
Shared
Memory
HEAR
Configurable
Accelerator
Boot ROM Battery
Monitor
CRC Generator
Analog
Inputs
Port
LSAD
Interrupt
Controller
2 or 5*
3 or 4*
4
IOC (Output Side)
Shared
Interface
(Output Side)
5
Preamplifier
Downsampling
4 or 5*
A/D
A/D
A/D
A/D
Output
Driver
BelaSigna 300
Preamplifier
Downsampling
*: Depending on package option
I
2
C
PCM/I
2
S
I
2
C Debug
PCM/I
2
S
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CFX DSP Core
The CFX DSP is a user−programmable general−purpose
DSP core that uses a 24−bit fixed−point, dual−MAC,
dual−Harvard architecture. It is able to perform two MACs,
two memory operations and two pointer updates per cycle,
making it well−suited to computationally intensive
algorithms.
The CFX features:
Dual−MAC 24−bit load−store DSP core
Four 56−bit accumulators
Four 24−bit input registers
Support for hardware loops nested up to 4 deep
Combined XY memory space (48−bits wide)
Dual address generator units
Wide range of addressing modes:
Direct
Indirect with post−modification
Modulo addressing
Bit reverse
CFX DSP Architecture
The CFX architecture encompasses various memory
types and sizes, peripherals, interrupt controllers, and
interfaces. Figure 3 illustrates the basic architecture of the
CFX. The control lines shown exiting the PCU indicate that
control signals go from the PCU to essentially all other parts
of the CFX.
The CFX employs a parallel instruction set for
simultaneous control of multiple computation units. The
DSP can execute up to four computation operations in
parallel with two data transfers (including rounding and/or
saturation as well as complex address updates), while
simultaneously changing control flow.
SR
LR
ILSR
ILPC
PC
PCU
CTRL
X0
X1
Pre−adder
X Multiplier
X ALU and
Shifter
A Accumulators
Y0
Y1
Y Multiplier
DCU
Y ALU
Immediate
Interrupts
CTRL
X Round/
Saturate
Y Round/
Saturate
X Sign/Zero
Extend
Y Sign/Zero
Extend
DMU
X Data
Y Data
SP Offset
Direct Addr
CTRL
PMEM
XMEM
YMEM
Internal Routing
Instruction Bus
P Bus
X Bus
Y Bus
Y Bus
X Bus
P Bus
Internal Routing
X AGU
Y AGU
Data registers
Address and Control registers
Hardware Loop
Stack
B Accumulators
Figure 3. CFX DSP Core Architecture

B300D44A102XXG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Audio DSPs BELASIGNA 300
Lifecycle:
New from this manufacturer.
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